{"id":"https://openalex.org/W2782120976","doi":"https://doi.org/10.1109/test.2017.8242041","title":"Front-end layout reflection for test chip design","display_name":"Front-end layout reflection for test chip design","publication_year":2017,"publication_date":"2017-10-01","ids":{"openalex":"https://openalex.org/W2782120976","doi":"https://doi.org/10.1109/test.2017.8242041","mag":"2782120976"},"language":"en","primary_location":{"id":"doi:10.1109/test.2017.8242041","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2017.8242041","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101673019","display_name":"Zeye Liu","orcid":"https://orcid.org/0000-0003-2516-3423"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Zeye Liu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036037496","display_name":"Phillip Fynan","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Phillip Fynan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111967389","display_name":"R.D. Blanton","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. D. Blanton","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, PA, US"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, PA, US","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101673019"],"corresponding_institution_ids":["https://openalex.org/I74973139"],"apc_list":null,"apc_paid":null,"fwci":0.9013,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.76354328,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"9871","issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6672643423080444},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6636431813240051},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6284575462341309},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6174283623695374},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.560875654220581},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5225857496261597},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5216610431671143},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.49953508377075195},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4766424596309662},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.44353145360946655},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.42763829231262207},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41076597571372986},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3800504505634308},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3640296459197998},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3620744049549103},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33220523595809937},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3163298964500427},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.27349841594696045},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23510169982910156},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1568218171596527},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12134113907814026}],"concepts":[{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6672643423080444},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6636431813240051},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6284575462341309},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6174283623695374},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.560875654220581},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5225857496261597},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5216610431671143},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.49953508377075195},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4766424596309662},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.44353145360946655},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.42763829231262207},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41076597571372986},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3800504505634308},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3640296459197998},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3620744049549103},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33220523595809937},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3163298964500427},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.27349841594696045},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23510169982910156},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1568218171596527},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12134113907814026},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2017.8242041","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2017.8242041","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5600000023841858,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W306641292","https://openalex.org/W1513771936","https://openalex.org/W1822750977","https://openalex.org/W1996239342","https://openalex.org/W2016381774","https://openalex.org/W2029130586","https://openalex.org/W2101631039","https://openalex.org/W2117477421","https://openalex.org/W2120391052","https://openalex.org/W2134289172","https://openalex.org/W2138275253","https://openalex.org/W2146232231","https://openalex.org/W2155042027","https://openalex.org/W2155298431","https://openalex.org/W2187831645","https://openalex.org/W2318561966","https://openalex.org/W2345901286","https://openalex.org/W2404369975","https://openalex.org/W2414406137","https://openalex.org/W2546147110","https://openalex.org/W2567791876","https://openalex.org/W2567901352","https://openalex.org/W6649165315","https://openalex.org/W6699962404","https://openalex.org/W6705108459","https://openalex.org/W6715617017"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W2142405811","https://openalex.org/W2114980936","https://openalex.org/W2164493372","https://openalex.org/W1594445436","https://openalex.org/W2128920253","https://openalex.org/W2164349885","https://openalex.org/W2124826473"],"abstract_inverted_index":{"Fast":[0],"yield":[1],"ramping":[2],"in":[3],"a":[4,13,33,46,66],"new":[5],"technology":[6],"to":[7],"meet":[8],"aggressive":[9],"time-to-market":[10],"deadlines":[11],"requires":[12],"comprehensive":[14],"design":[15,67,95],"and":[16,26,57,61,79,88,96],"fabrication":[17],"methodology":[18],"for":[19],"silicon":[20],"test":[21,47,82,93],"structures":[22],"that":[23,44,49,53,69],"systematically":[24],"explores":[25],"validates":[27],"the":[28,92,101],"technology.":[29],"Prior":[30],"work":[31,64],"proposed":[32],"novel":[34],"logic":[35,51,87],"characterization":[36],"vehicle":[37],"(LCV),":[38],"along":[39],"with":[40],"an":[41,76],"implementation":[42],"flow":[43,68],"produces":[45],"chip":[48,94],"ensures":[50,58],"demographics":[52],"resemble":[54],"real":[55],"products,":[56],"near-optimal":[59],"testability":[60],"diagnosability.":[62],"This":[63],"describes":[65],"efficiently":[70],"incorporates":[71],"FEOL":[72],"layout":[73,89],"properties":[74,90],"into":[75],"easily":[77],"testable":[78],"diagnosable":[80],"logic-based":[81],"chip.":[83],"Experiments":[84],"comparing":[85],"testability,":[86],"between":[91],"various":[97],"benchmark":[98],"circuits":[99],"demonstrate":[100],"efficacy":[102],"of":[103],"this":[104],"approach.":[105]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}