{"id":"https://openalex.org/W2570911459","doi":"https://doi.org/10.1109/test.2016.7805831","title":"Fault simulation for analog test coverage","display_name":"Fault simulation for analog test coverage","publication_year":2016,"publication_date":"2016-11-01","ids":{"openalex":"https://openalex.org/W2570911459","doi":"https://doi.org/10.1109/test.2016.7805831","mag":"2570911459"},"language":"en","primary_location":{"id":"doi:10.1109/test.2016.7805831","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2016.7805831","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078675590","display_name":"Jyotsna Sequeira","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Jyotsna Sequeira","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113724917","display_name":"Suriyaprakash Natarajan","orcid":"https://orcid.org/0000-0002-5499-4341"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Suriyaprakash Natarajan","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005439185","display_name":"Prashant Goteti","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Prashant Goteti","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005961179","display_name":"Nitin Chaudhary","orcid":"https://orcid.org/0000-0003-3542-8157"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Nitin Chaudhary","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9614,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.75941765,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.71638023853302},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.7045396566390991},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6186762452125549},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.6109490990638733},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.6015992760658264},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5555002093315125},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.551234245300293},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5112495422363281},{"id":"https://openalex.org/keywords/stuck-at-fault","display_name":"Stuck-at fault","score":0.47234928607940674},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4416041076183319},{"id":"https://openalex.org/keywords/fault-detection-and-isolation","display_name":"Fault detection and isolation","score":0.4404029846191406},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.41712355613708496},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.41604623198509216},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4077393710613251},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34154993295669556},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2970069646835327},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2919405996799469},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16915348172187805},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.07901561260223389}],"concepts":[{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.71638023853302},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.7045396566390991},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6186762452125549},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.6109490990638733},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.6015992760658264},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5555002093315125},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.551234245300293},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5112495422363281},{"id":"https://openalex.org/C13625343","wikidata":"https://www.wikidata.org/wiki/Q7627418","display_name":"Stuck-at fault","level":4,"score":0.47234928607940674},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4416041076183319},{"id":"https://openalex.org/C152745839","wikidata":"https://www.wikidata.org/wiki/Q5438153","display_name":"Fault detection and isolation","level":3,"score":0.4404029846191406},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.41712355613708496},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.41604623198509216},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4077393710613251},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34154993295669556},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2970069646835327},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2919405996799469},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16915348172187805},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.07901561260223389},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C172707124","wikidata":"https://www.wikidata.org/wiki/Q423488","display_name":"Actuator","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2016.7805831","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2016.7805831","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1563273748","https://openalex.org/W1686846969","https://openalex.org/W1874000772","https://openalex.org/W1980392502","https://openalex.org/W1993765721","https://openalex.org/W1999141085","https://openalex.org/W2034650804","https://openalex.org/W2044302877","https://openalex.org/W2065680840","https://openalex.org/W2073654891","https://openalex.org/W2088797164","https://openalex.org/W2098112833","https://openalex.org/W2101456051","https://openalex.org/W2106816366","https://openalex.org/W2106868151","https://openalex.org/W2113234369","https://openalex.org/W2116080338","https://openalex.org/W2124017175","https://openalex.org/W2135282447","https://openalex.org/W2155221776","https://openalex.org/W2162571237","https://openalex.org/W2165015944","https://openalex.org/W4235485521","https://openalex.org/W4244195727","https://openalex.org/W4247060235","https://openalex.org/W4253563432","https://openalex.org/W6669057211","https://openalex.org/W6680411426"],"related_works":["https://openalex.org/W2340957901","https://openalex.org/W4242258007","https://openalex.org/W2155285526","https://openalex.org/W2007222089","https://openalex.org/W2092357065","https://openalex.org/W2115005577","https://openalex.org/W2068571131","https://openalex.org/W2147400189","https://openalex.org/W1555400249","https://openalex.org/W1578030032"],"abstract_inverted_index":{"A":[0,32],"practical":[1],"fault":[2,26,96],"simulation":[3,18,27],"methodology":[4,14],"for":[5],"analog":[6,30],"circuits":[7],"in":[8,49,61,95],"mixed-signal":[9,17,25],"designs":[10],"is":[11],"presented.":[12],"The":[13],"leverages":[15],"the":[16,51,62,80,90],"environment":[19],"of":[20,28,34,56,64,82,92],"a":[21,65],"product":[22],"and":[23,36,46,89],"performs":[24],"embedded":[29],"circuits.":[31],"set":[33],"open-circuit":[35],"short-circuit":[37],"faults":[38,60],"are":[39,71],"extracted":[40],"with":[41,73],"guidance":[42],"from":[43],"layout":[44],"parasitics,":[45],"automatically":[47],"injected":[48],"to":[50],"net":[52],"list.":[53],"Fault":[54],"coverage":[55],"manufacturing":[57],"tests":[58],"on":[59],"transmitter":[63],"high":[66],"speed":[67],"serial":[68],"interface":[69],"design":[70],"reported":[72],"two":[74],"different":[75],"observation":[76,94],"criteria.":[77],"Results":[78],"indicate":[79],"amount":[81],"test":[83],"reduction":[84],"that":[85],"can":[86],"be":[87],"achieved":[88],"importance":[91],"appropriate":[93],"detection.":[97]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}