{"id":"https://openalex.org/W2182512273","doi":"https://doi.org/10.1109/test.2015.7342405","title":"On diagnosable and tunable 3D clock network design for lifetime reliability enhancement","display_name":"On diagnosable and tunable 3D clock network design for lifetime reliability enhancement","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W2182512273","doi":"https://doi.org/10.1109/test.2015.7342405","mag":"2182512273"},"language":"en","primary_location":{"id":"doi:10.1109/test.2015.7342405","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2015.7342405","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053801300","display_name":"Li Jiang","orcid":"https://orcid.org/0000-0002-7353-8798"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Li Jiang","raw_affiliation_strings":["Department of CS&E, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of CS&E, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083883541","display_name":"Pu Pang","orcid":"https://orcid.org/0009-0004-3685-0901"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Pu Pang","raw_affiliation_strings":["Department of CS&E, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of CS&E, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045693138","display_name":"Naifeng Jing","orcid":"https://orcid.org/0000-0001-8417-5796"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Naifeng Jing","raw_affiliation_strings":["Department of CS&E, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of CS&E, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052950521","display_name":"Sung Kyu Lim","orcid":"https://orcid.org/0000-0002-2267-5282"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung Kyu Lim","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, GA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, GA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056632010","display_name":"Xiaoyao Liang","orcid":"https://orcid.org/0000-0002-2790-5884"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyao Liang","raw_affiliation_strings":["Department of CS&E, Shanghai Jiao Tong University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Department of CS&E, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088556682","display_name":"Qiang Xu","orcid":"https://orcid.org/0000-0001-6747-126X"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiang Xu","raw_affiliation_strings":["Department of CS&E, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of CS&E, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5053801300"],"corresponding_institution_ids":["https://openalex.org/I183067930"],"apc_list":null,"apc_paid":null,"fwci":0.1973,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.59026549,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"32","issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6603193283081055},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6368744373321533},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5959082841873169},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5863058567047119},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5619152188301086},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.4946148097515106},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.4595900774002075},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4393404424190521},{"id":"https://openalex.org/keywords/rendering","display_name":"Rendering (computer graphics)","score":0.43572190403938293},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4335099458694458},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.4236375689506531},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3987996578216553},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3900267481803894},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38932839035987854},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.33701473474502563},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19596481323242188},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18239110708236694},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.1590338945388794}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6603193283081055},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6368744373321533},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5959082841873169},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5863058567047119},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5619152188301086},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.4946148097515106},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.4595900774002075},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4393404424190521},{"id":"https://openalex.org/C205711294","wikidata":"https://www.wikidata.org/wiki/Q176953","display_name":"Rendering (computer graphics)","level":2,"score":0.43572190403938293},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4335099458694458},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.4236375689506531},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3987996578216553},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3900267481803894},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38932839035987854},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.33701473474502563},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19596481323242188},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18239110708236694},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.1590338945388794},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2015.7342405","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2015.7342405","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1514437667","https://openalex.org/W1964664019","https://openalex.org/W1968812826","https://openalex.org/W1977325223","https://openalex.org/W1981790341","https://openalex.org/W1987131925","https://openalex.org/W1987638749","https://openalex.org/W2001560636","https://openalex.org/W2005613478","https://openalex.org/W2043843580","https://openalex.org/W2072609296","https://openalex.org/W2086481541","https://openalex.org/W2092824166","https://openalex.org/W2107868198","https://openalex.org/W2108852347","https://openalex.org/W2111971510","https://openalex.org/W2119986070","https://openalex.org/W2122915341","https://openalex.org/W2131875329","https://openalex.org/W2132333357","https://openalex.org/W2141565132","https://openalex.org/W2149864516","https://openalex.org/W2154517054","https://openalex.org/W2156064231","https://openalex.org/W2158473722","https://openalex.org/W2164217202","https://openalex.org/W3146255990","https://openalex.org/W3148981577","https://openalex.org/W4230375614","https://openalex.org/W4233474994","https://openalex.org/W4236597533","https://openalex.org/W4243059613","https://openalex.org/W6650654555","https://openalex.org/W6653704599","https://openalex.org/W6682236896","https://openalex.org/W6682867480"],"related_works":["https://openalex.org/W2174922170","https://openalex.org/W2133326759","https://openalex.org/W3006003651","https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2040807843","https://openalex.org/W1564063853","https://openalex.org/W4230501858","https://openalex.org/W2559451387","https://openalex.org/W4249038728"],"abstract_inverted_index":{"In":[0],"three-dimensional":[1],"(3D)":[2],"integrated":[3],"circuits":[4],"(IC-s),":[5],"many":[6],"clock-TSVs":[7,22],"are":[8,23],"deployed":[9],"to":[10,14,25,75,86,102,148],"deliver":[11],"clock":[12,36,95,122],"signals":[13],"different":[15],"tiers":[16],"with":[17],"minimum":[18],"skews.":[19],"However,":[20],"these":[21],"prone":[24],"aging":[26,66,104,132],"effects,":[27],"such":[28],"as":[29],"thermal-mechanical":[30],"stress":[31],"and":[32,51,97,119],"electromigration,":[33],"rendering":[34],"hard-to-predict":[35],"skews":[37,41,71],"at":[38,109,113],"runtime.":[39],"These":[40],"have":[42],"a":[43,137],"wide":[44],"range":[45],"of":[46,57,154],"influence":[47],"on":[48,126,136],"the":[49,54,61,64,68,76,94,107,127,131,143,151],"flip-flops,":[50],"may":[52],"violate":[53],"safety":[55],"margins":[56],"critical":[58],"paths":[59],"in":[60,93,106,130],"circuit.":[62],"Besides":[63],"circuit":[65,77,108,140],"effect,":[67],"clock-TSV":[69,92],"induced":[70],"pose":[72],"another":[73],"threat":[74],"lifetime":[78,152],"reliability.":[79],"To":[80],"tackle":[81],"this":[82],"problem,":[83],"we":[84,115],"propose":[85],"put":[87],"tunable":[88],"buffer":[89],"for":[90],"each":[91],"network,":[96],"introduce":[98],"an":[99],"efficient":[100],"algorithm":[101],"place":[103],"sensors":[105],"design":[110],"stage.":[111],"Then,":[112],"runtime,":[114],"conduct":[116],"online":[117],"diagnosis":[118],"apply":[120],"effective":[121],"tuning":[123],"algorithms":[124],"based":[125],"triggered":[128],"alarms":[129],"sensors.":[133],"Experimental":[134],"results":[135],"post-layout":[138],"3D":[139,155],"show":[141],"that":[142],"proposed":[144],"solution":[145],"is":[146],"able":[147],"significantly":[149],"improve":[150],"reliability":[153],"ICs.":[156]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}