{"id":"https://openalex.org/W2185119483","doi":"https://doi.org/10.1109/test.2015.7342399","title":"Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine","display_name":"Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W2185119483","doi":"https://doi.org/10.1109/test.2015.7342399","mag":"2185119483"},"language":"en","primary_location":{"id":"doi:10.1109/test.2015.7342399","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2015.7342399","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070135749","display_name":"Bruce Querbach","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Bruce Querbach","raw_affiliation_strings":["Intel, Hillsboro, Oregon, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, Oregon, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060324924","display_name":"Tan Peter Yanyang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tan Peter Yanyang","raw_affiliation_strings":["Intel, Hillsboro, Oregon, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, Oregon, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036656550","display_name":"Lovelace Van","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lovelace Van","raw_affiliation_strings":["Intel, Hillsboro, Oregon, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, Oregon, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086873963","display_name":"David Blankenbeckler","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Blankenbeckler","raw_affiliation_strings":["Intel, Hillsboro, Oregon, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, Oregon, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038426107","display_name":"Rahul Khanna","orcid":"https://orcid.org/0000-0001-8101-4655"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rahul Khanna","raw_affiliation_strings":["Intel, Hillsboro, Oregon, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, Oregon, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070779291","display_name":"Sudeep Puligundla","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudeep Puligundla","raw_affiliation_strings":["Intel, Hillsboro, Oregon, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, Oregon, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112245798","display_name":"Patrick Yin Chiang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Patrick Chiang","raw_affiliation_strings":["Intel, Hillsboro, Oregon, USA"],"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, Oregon, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5070135749"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.0979544,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"6","issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7678916454315186},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6647769212722778},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.640244722366333},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.48750802874565125},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4716562330722809},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.4518154263496399},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.42792055010795593},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36042308807373047},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3496890962123871},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.3102640211582184}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7678916454315186},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6647769212722778},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.640244722366333},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.48750802874565125},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4716562330722809},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.4518154263496399},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.42792055010795593},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36042308807373047},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3496890962123871},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.3102640211582184}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2015.7342399","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2015.7342399","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6299999952316284,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1026930949","https://openalex.org/W1592248212","https://openalex.org/W1995460436","https://openalex.org/W2007743660","https://openalex.org/W2042667731","https://openalex.org/W2058546038","https://openalex.org/W2059740885","https://openalex.org/W2103477679","https://openalex.org/W2119913792","https://openalex.org/W2122249806","https://openalex.org/W2127512823","https://openalex.org/W2129452807","https://openalex.org/W2136559078","https://openalex.org/W2156272194","https://openalex.org/W2245396909","https://openalex.org/W2298698312","https://openalex.org/W2302993541","https://openalex.org/W6679328324","https://openalex.org/W6680303280"],"related_works":["https://openalex.org/W2167303720","https://openalex.org/W2012518269","https://openalex.org/W4243772489","https://openalex.org/W57688818","https://openalex.org/W2109715593","https://openalex.org/W1963899689","https://openalex.org/W4226093591","https://openalex.org/W4246122698","https://openalex.org/W1581731722","https://openalex.org/W2363750085"],"abstract_inverted_index":{"As":[0],"the":[1,41,49,103,110],"memory":[2,7,56,78],"industry":[3],"pushes":[4],"to":[5,34,47,52,93,96,133,145],"increase":[6],"density,":[8],"device":[9],"variation":[10],"is":[11,57],"creating":[12],"more":[13],"defects.":[14],"Furthermore,":[15],"new":[16],"form":[17],"factors":[18],"(phone,":[19],"tablet,":[20],"mobile":[21],"and":[22,25,29,54,63,116,124,141],"client":[23],"PC)":[24],"low":[26],"cost":[27],"board":[28],"platform":[30],"limits":[31],"physical":[32],"access":[33,53],"JTAG":[35,97,134],"or":[36,98,135],"TAP.":[37,136],"Taking":[38],"advantage":[39],"of":[40,130],"x86":[42],"architecture's":[43],"high":[44],"functional":[45],"bandwidth":[46],"memory,":[48],"quickest":[50],"way":[51],"test":[55,67,90,105,113,121,131],"through":[58],"CPU":[59,70],"core,":[60],"by":[61,127],"storing":[62],"running":[64],"parallel":[65],"CPGC/BIST":[66],"content":[68],"via":[69],"L3":[71],"cache,":[72],"one":[73],"CPGC":[74],"BIST":[75],"engine":[76],"per":[77],"channel.":[79],"We":[80,107],"propose":[81],"a":[82,125],"cache":[83,111,147],"based":[84,100,112,148],"testing":[85,101],"framework":[86],"that":[87],"speeds":[88],"up":[89],"time":[91,132],"60\u00d7":[92],"170\u00d7":[94],"compared":[95],"TAP":[99],"using":[102],"same":[104],"content.":[106],"will":[108,139],"present":[109],"(CBT)":[114],"architecture":[115],"infrastructure":[117],"(MRC/NEM":[118],"setup,":[119],"CPGC/IBIST),":[120],"content,":[122],"results,":[123],"side":[126,128],"comparison":[129],"Finally":[137],"we":[138],"discuss":[140],"compare":[142],"this":[143],"approach":[144],"generalized":[146],"tests.":[149]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
