{"id":"https://openalex.org/W1981661491","doi":"https://doi.org/10.1109/test.2013.6651930","title":"Design rule check on the clock gating logic for testability and beyond","display_name":"Design rule check on the clock gating logic for testability and beyond","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W1981661491","doi":"https://doi.org/10.1109/test.2013.6651930","mag":"1981661491"},"language":"en","primary_location":{"id":"doi:10.1109/test.2013.6651930","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2013.6651930","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064587514","display_name":"Kun-Han Tsai","orcid":"https://orcid.org/0000-0001-8919-8663"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kun-Han Tsai","raw_affiliation_strings":["Silicon Test Solutions, Mentor Graphics, Wilsonville, Oregon, USA","Mentor Graphics, Silicon Test Solutions, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Test Solutions, Mentor Graphics, Wilsonville, Oregon, USA","institution_ids":[]},{"raw_affiliation_string":"Mentor Graphics, Silicon Test Solutions, Wilsonville, OR, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025112777","display_name":"Shuo Sheng","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shuo Sheng","raw_affiliation_strings":["Silicon Test Solutions, Mentor Graphics, Wilsonville, Oregon, USA","Mentor Graphics, Silicon Test Solutions, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Test Solutions, Mentor Graphics, Wilsonville, Oregon, USA","institution_ids":[]},{"raw_affiliation_string":"Mentor Graphics, Silicon Test Solutions, Wilsonville, OR, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7634212374687195},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.707757294178009},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6600950956344604},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6190449595451355},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5399717092514038},{"id":"https://openalex.org/keywords/voltage-droop","display_name":"Voltage droop","score":0.5305082201957703},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.48786067962646484},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.44580990076065063},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.43624040484428406},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4180067777633667},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4134748578071594},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3790943920612335},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3576851785182953},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35196924209594727},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2799367308616638},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2578057646751404},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.22154471278190613},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.17365658283233643},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11986240744590759},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.11504244804382324},{"id":"https://openalex.org/keywords/voltage-regulator","display_name":"Voltage regulator","score":0.080119788646698}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7634212374687195},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.707757294178009},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6600950956344604},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6190449595451355},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5399717092514038},{"id":"https://openalex.org/C40760162","wikidata":"https://www.wikidata.org/wiki/Q10920295","display_name":"Voltage droop","level":4,"score":0.5305082201957703},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.48786067962646484},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.44580990076065063},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.43624040484428406},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4180067777633667},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4134748578071594},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3790943920612335},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3576851785182953},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35196924209594727},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2799367308616638},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2578057646751404},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.22154471278190613},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.17365658283233643},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11986240744590759},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.11504244804382324},{"id":"https://openalex.org/C110706871","wikidata":"https://www.wikidata.org/wiki/Q851210","display_name":"Voltage regulator","level":3,"score":0.080119788646698},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2013.6651930","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2013.6651930","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W14634279","https://openalex.org/W2102015257","https://openalex.org/W2130632823","https://openalex.org/W2137271566","https://openalex.org/W2137310043","https://openalex.org/W2139098514","https://openalex.org/W2143817030","https://openalex.org/W2144746612"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W2142405811","https://openalex.org/W2114980936","https://openalex.org/W2164493372","https://openalex.org/W1594445436","https://openalex.org/W2168652618","https://openalex.org/W2127247647","https://openalex.org/W2166402441"],"abstract_inverted_index":{"The":[0,33],"paper":[1],"describes":[2],"clock":[3],"gating":[4],"structures":[5],"in":[6],"practice":[7],"that":[8],"can":[9],"impact":[10],"the":[11,19,30,50,61,73],"testability":[12],"and":[13,29,43],"cause":[14],"silicon":[15],"failure":[16],"due":[17],"to":[18,41,59,67],"race":[20],"condition":[21],"or":[22],"timing":[23],"uncertainty":[24],"such":[25,46,64],"as":[26],"voltage":[27],"droop":[28],"process":[31],"variations.":[32],"design":[34,62],"rule":[35,65],"check":[36],"(DRC)":[37],"algorithm":[38],"is":[39,57],"presented":[40],"efficiently":[42],"robustly":[44],"identify":[45],"problematic":[47],"structures.":[48],"Furthermore,":[49],"automatic":[51],"test":[52,74],"pattern":[53],"generation":[54],"(ATPG)":[55],"method":[56],"proposed":[58],"handle":[60],"with":[63],"violations":[66],"prevent":[68],"simulation":[69],"mismatches":[70],"while":[71],"minimizing":[72],"coverage":[75],"lost.":[76]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
