{"id":"https://openalex.org/W2048968819","doi":"https://doi.org/10.1109/test.2013.6651897","title":"SmartScan - Hierarchical test compression for pin-limited low power designs","display_name":"SmartScan - Hierarchical test compression for pin-limited low power designs","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2048968819","doi":"https://doi.org/10.1109/test.2013.6651897","mag":"2048968819"},"language":"en","primary_location":{"id":"doi:10.1109/test.2013.6651897","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2013.6651897","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016355921","display_name":"Krishna Chakravadhanula","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"K. Chakravadhanula","raw_affiliation_strings":["Encounter Test R&D, Cadence Design Systems, NY, USA","Encounter Test R&D, Cadence Design Syst., Endicott, NY, USA"],"affiliations":[{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Systems, NY, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Syst., Endicott, NY, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061006452","display_name":"Vivek Chickermane","orcid":"https://orcid.org/0000-0003-1232-470X"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V. Chickermane","raw_affiliation_strings":["Encounter Test R&D, Cadence Design Systems, NY, USA","Encounter Test R&D, Cadence Design Syst., Endicott, NY, USA"],"affiliations":[{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Systems, NY, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Syst., Endicott, NY, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037560245","display_name":"D. Pearl","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Pearl","raw_affiliation_strings":["Encounter Test R&D, Cadence Design Systems, NY, USA","Encounter Test R&D, Cadence Design Syst., Endicott, NY, USA"],"affiliations":[{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Systems, NY, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Syst., Endicott, NY, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012030397","display_name":"Atul Garg","orcid":"https://orcid.org/0000-0001-5853-3051"},"institutions":[{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. Garg","raw_affiliation_strings":["Encounter Test R&D, Cadence Design Systems, Noida, UP, India","Encounter Test R&D, Cadence Design Syst., Noida, India"],"affiliations":[{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Systems, Noida, UP, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Syst., Noida, India","institution_ids":["https://openalex.org/I4210111610"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017169003","display_name":"Ravi khurana","orcid":null},"institutions":[{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. Khurana","raw_affiliation_strings":["Encounter Test R&D, Cadence Design Systems, Noida, UP, India","Encounter Test R&D, Cadence Design Syst., Noida, India"],"affiliations":[{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Systems, Noida, UP, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Syst., Noida, India","institution_ids":["https://openalex.org/I4210111610"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109158893","display_name":"Subhasish Mukherjee","orcid":null},"institutions":[{"id":"https://openalex.org/I4210111610","display_name":"Cadence Design Systems (India)","ror":"https://ror.org/027qdw603","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210111610","https://openalex.org/I66217453"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Mukherjee","raw_affiliation_strings":["Encounter Test R&D, Cadence Design Systems, Noida, UP, India","Encounter Test R&D, Cadence Design Syst., Noida, India"],"affiliations":[{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Systems, Noida, UP, India","institution_ids":["https://openalex.org/I4210111610"]},{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Syst., Noida, India","institution_ids":["https://openalex.org/I4210111610"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084415408","display_name":"P. Nagaraj","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Nagaraj","raw_affiliation_strings":["Encounter Test R&D, Cadence Design Systems, San Jose, CA, USA","Encounter Test R&D, Cadence Design Syst., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Systems, San Jose, CA, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Encounter Test R&D, Cadence Design Syst., San Jose, CA, USA","institution_ids":["https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5016355921"],"corresponding_institution_ids":["https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":3.7825,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.93322025,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6798382997512817},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6609050035476685},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6430971026420593},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6197614669799805},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4566686451435089},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.42567822337150574},{"id":"https://openalex.org/keywords/compression","display_name":"Compression (physics)","score":0.4250001311302185},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.42253953218460083},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4063764810562134},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18995708227157593},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.07304883003234863},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.07145217061042786}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6798382997512817},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6609050035476685},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6430971026420593},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6197614669799805},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4566686451435089},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.42567822337150574},{"id":"https://openalex.org/C180016635","wikidata":"https://www.wikidata.org/wiki/Q2712821","display_name":"Compression (physics)","level":2,"score":0.4250001311302185},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.42253953218460083},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4063764810562134},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18995708227157593},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.07304883003234863},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.07145217061042786},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2013.6651897","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2013.6651897","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE International Test Conference (ITC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1592824829","https://openalex.org/W1863819993","https://openalex.org/W2105282021","https://openalex.org/W2110267158","https://openalex.org/W2112041422","https://openalex.org/W2114584148","https://openalex.org/W2127737927","https://openalex.org/W2130408546","https://openalex.org/W2136575309","https://openalex.org/W2139009001","https://openalex.org/W4210799017"],"related_works":["https://openalex.org/W2005401624","https://openalex.org/W2038886877","https://openalex.org/W2550015578","https://openalex.org/W2167255265","https://openalex.org/W2160753176","https://openalex.org/W2032893376","https://openalex.org/W2569480541","https://openalex.org/W2153702200","https://openalex.org/W2129286312","https://openalex.org/W2002185056"],"abstract_inverted_index":{"IP":[0],"cores":[1,15],"that":[2,36,59,73],"are":[3,16],"embedded":[4,9,17,50],"in":[5,18,83],"SoCs":[6],"usually":[7],"include":[8],"test":[10,39,88],"compression":[11],"hardware.":[12],"When":[13],"multiple":[14],"a":[19,27,30,56,84],"SoC":[20,87],"with":[21,90],"limited":[22],"tester-contacted":[23],"pins,":[24],"there":[25],"is":[26,60],"need":[28],"for":[29],"structured":[31],"test-access":[32],"mechanism":[33],"(TAM)":[34],"architecture":[35,58],"allows":[37],"compressed":[38,66,76],"data":[40],"stimuli":[41],"and":[42],"responses":[43],"to":[44,48],"be":[45,80],"efficiently":[46,81],"distributed":[47],"the":[49],"cores.":[51],"This":[52],"paper":[53],"presents":[54],"SmartScan,":[55],"TAM":[57],"based":[61],"on":[62,69],"time-domain":[63],"multiplexing":[64],"of":[65],"data.":[67],"Results":[68],"industrial":[70],"designs":[71],"show":[72],"high":[74],"quality":[75],"ATPG":[77],"patterns":[78],"can":[79],"re-applied":[82],"very":[85,91],"low-pin":[86],"environment":[89],"low":[92],"overhead.":[93]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}