{"id":"https://openalex.org/W2067246568","doi":"https://doi.org/10.1109/test.2012.6401582","title":"A design flow to maximize yield/area of physical devices via redundancy","display_name":"A design flow to maximize yield/area of physical devices via redundancy","publication_year":2012,"publication_date":"2012-11-01","ids":{"openalex":"https://openalex.org/W2067246568","doi":"https://doi.org/10.1109/test.2012.6401582","mag":"2067246568"},"language":"en","primary_location":{"id":"doi:10.1109/test.2012.6401582","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2012.6401582","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073682085","display_name":"Mohammad Mirza-Aghatabar","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mohammad Mirza-Aghatabar","raw_affiliation_strings":["Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA","Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA#TAB#","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110173607","display_name":"Melvin A. Breuer","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Melvin A. Breuer","raw_affiliation_strings":["Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA","Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA#TAB#","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100601790","display_name":"Sandeep K. Gupta","orcid":"https://orcid.org/0000-0002-2585-9378"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sandeep K. Gupta","raw_affiliation_strings":["Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA","Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA#TAB#","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5073682085"],"corresponding_institution_ids":["https://openalex.org/I1174212"],"apc_list":null,"apc_paid":null,"fwci":0.5801,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.67453626,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.7537021636962891},{"id":"https://openalex.org/keywords/granularity","display_name":"Granularity","score":0.6683925986289978},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5964510440826416},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5613493919372559},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5541170239448547},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5391521453857422},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5190058946609497},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4844553470611572},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.44092458486557007},{"id":"https://openalex.org/keywords/spare-part","display_name":"Spare part","score":0.43845948576927185},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.436308890581131},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4225732982158661},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4159424304962158},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.388996958732605},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35414204001426697},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.27546384930610657},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2708149552345276},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22573965787887573},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21369364857673645},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.17570555210113525}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.7537021636962891},{"id":"https://openalex.org/C177774035","wikidata":"https://www.wikidata.org/wiki/Q1246948","display_name":"Granularity","level":2,"score":0.6683925986289978},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5964510440826416},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5613493919372559},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5541170239448547},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5391521453857422},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5190058946609497},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4844553470611572},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.44092458486557007},{"id":"https://openalex.org/C194648553","wikidata":"https://www.wikidata.org/wiki/Q1364774","display_name":"Spare part","level":2,"score":0.43845948576927185},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.436308890581131},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4225732982158661},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4159424304962158},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.388996958732605},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35414204001426697},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.27546384930610657},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2708149552345276},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22573965787887573},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21369364857673645},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.17570555210113525},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2012.6401582","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2012.6401582","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4399999976158142}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1503570386","https://openalex.org/W1525100466","https://openalex.org/W1554885925","https://openalex.org/W1607915263","https://openalex.org/W1972251590","https://openalex.org/W1983476606","https://openalex.org/W1986563496","https://openalex.org/W2021792911","https://openalex.org/W2046045084","https://openalex.org/W2101241869","https://openalex.org/W2104193172","https://openalex.org/W2110834192","https://openalex.org/W2125067970","https://openalex.org/W2125890858","https://openalex.org/W2126696437","https://openalex.org/W2130327678","https://openalex.org/W2135123845","https://openalex.org/W2144382742","https://openalex.org/W2147142618","https://openalex.org/W2151913116","https://openalex.org/W2155038322","https://openalex.org/W2157259709","https://openalex.org/W2157838218","https://openalex.org/W2161704054","https://openalex.org/W2167933505","https://openalex.org/W2171340263","https://openalex.org/W2546394767","https://openalex.org/W2889404990","https://openalex.org/W3139734642","https://openalex.org/W4233714602","https://openalex.org/W4235837895","https://openalex.org/W4243134243","https://openalex.org/W4251528866","https://openalex.org/W6633069435"],"related_works":["https://openalex.org/W2227166741","https://openalex.org/W2543290882","https://openalex.org/W2735446578","https://openalex.org/W2246407281","https://openalex.org/W1989216432","https://openalex.org/W2292717402","https://openalex.org/W2146286671","https://openalex.org/W4247095439","https://openalex.org/W2269276134","https://openalex.org/W4241206086"],"abstract_inverted_index":{"This":[0],"paper":[1,53],"deals":[2],"with":[3,80,181],"using":[4,118],"redundancy":[5,119],"to":[6,25,31,64,69,139,148,188],"maximize":[7,149],"the":[8,43,56,126,136,141,162,165,170,177],"number":[9],"of":[10,51,60,87,98,123,135,144,172,196],"\u201cworkable\u201d":[11],"die":[12],"one":[13],"can":[14],"produce":[15],"from":[16],"a":[17,77,88,99,152,194],"silicon":[18],"wafer.":[19],"When":[20],"redundant":[21,179],"modules":[22,66],"are":[23,68],"used":[24],"enhance":[26],"yield,":[27],"several":[28],"issues":[29],"need":[30],"be":[32,70],"addressed,":[33],"such":[34,110],"as":[35,111,193],"power,":[36],"performance":[37],"degradation,":[38],"testability,":[39],"area,":[40],"and":[41,62,107,114,157],"partitioning":[42,61,89,104],"original":[44],"logic":[45,95,101],"design":[46,78,106,154,174,180],"into":[47],"modules.":[48],"The":[49,83],"focus":[50],"this":[52,73],"is":[54],"on":[55],"long":[57],"ignored":[58],"issue":[59],"clustering":[63],"form":[65],"that":[67,91,169],"replicated.":[71],"For":[72],"purpose":[74],"we":[75,129,185],"propose":[76],"flow":[79,175],"two":[81],"phases.":[82],"first":[84],"phase":[85,128],"consists":[86],"process":[90],"generates":[92],"all":[93],"combinational":[94],"blocks":[96],"(CLBs)":[97],"given":[100],"circuit.":[102],"CLB":[103],"addresses":[105],"test":[108],"constraints":[109],"timing":[112],"closure":[113],"testing":[115],"complexity,":[116],"by":[117],"at":[120],"finer":[121],"levels":[122],"granularity.":[124],"In":[125],"second":[127],"carry":[130],"out":[131],"an":[132],"overall":[133],"optimization":[134],"generated":[137],"CLBs":[138],"find":[140],"optimal":[142],"level":[143],"granularity":[145],"for":[146],"replication":[147],"yield/area.":[150],"Using":[151],"real":[153],"(OpenSPARC":[155],"T2)":[156],"defect":[158,197],"densities":[159],"projected":[160],"in":[161],"near":[163],"future,":[164],"experimental":[166],"results":[167],"show":[168],"output":[171],"our":[173],"outperforms":[176],"traditional":[178],"spare":[182],"core,":[183],"e.g.":[184],"achieved":[186],"1.1":[187],"13.3":[189],"times":[190],"better":[191],"yield/area":[192],"function":[195],"density.":[198]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
