{"id":"https://openalex.org/W2054325167","doi":"https://doi.org/10.1109/test.2011.6139173","title":"Die-level adaptive test: Real-time test reordering and elimination","display_name":"Die-level adaptive test: Real-time test reordering and elimination","publication_year":2011,"publication_date":"2011-09-01","ids":{"openalex":"https://openalex.org/W2054325167","doi":"https://doi.org/10.1109/test.2011.6139173","mag":"2054325167"},"language":"en","primary_location":{"id":"doi:10.1109/test.2011.6139173","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2011.6139173","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032620780","display_name":"Kapil Gotkhindikar","orcid":null},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"K. R. Gotkhindikar","raw_affiliation_strings":["Integrated Circuits Design and Test Laboratory, Portland State University, Portland, OR, USA","Integrated Circuits Design and Test Laboratory, Portland State University, Portland,#TAB#"],"affiliations":[{"raw_affiliation_string":"Integrated Circuits Design and Test Laboratory, Portland State University, Portland, OR, USA","institution_ids":["https://openalex.org/I126345244"]},{"raw_affiliation_string":"Integrated Circuits Design and Test Laboratory, Portland State University, Portland,#TAB#","institution_ids":["https://openalex.org/I126345244"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001994622","display_name":"W.R. Daasch","orcid":null},"institutions":[{"id":"https://openalex.org/I126345244","display_name":"Portland State University","ror":"https://ror.org/00yn2fy02","country_code":"US","type":"education","lineage":["https://openalex.org/I126345244"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W. R. Daasch","raw_affiliation_strings":["Integrated Circuits Design and Test Laboratory, Portland State University, Portland, OR, USA","Integrated Circuits Design and Test Laboratory, Portland State University, Portland,#TAB#"],"affiliations":[{"raw_affiliation_string":"Integrated Circuits Design and Test Laboratory, Portland State University, Portland, OR, USA","institution_ids":["https://openalex.org/I126345244"]},{"raw_affiliation_string":"Integrated Circuits Design and Test Laboratory, Portland State University, Portland,#TAB#","institution_ids":["https://openalex.org/I126345244"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110130179","display_name":"Kenneth M. Butler","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. M. Butler","raw_affiliation_strings":["Texas Instrumenits, Inc., Dallas, TX, USA","Texas Instruments Dallas, TX"],"affiliations":[{"raw_affiliation_string":"Texas Instrumenits, Inc., Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111"]},{"raw_affiliation_string":"Texas Instruments Dallas, TX","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039431688","display_name":"John M. Carulli","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. M. Carulli","raw_affiliation_strings":["Texas Instrumenits, Inc., Dallas, TX, USA","Texas Instruments Dallas, TX"],"affiliations":[{"raw_affiliation_string":"Texas Instrumenits, Inc., Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111"]},{"raw_affiliation_string":"Texas Instruments Dallas, TX","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111905813","display_name":"Amit Nahar","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Nahar","raw_affiliation_strings":["Texas Instrumenits, Inc., Dallas, TX, USA","Texas Instruments Dallas, TX"],"affiliations":[{"raw_affiliation_string":"Texas Instrumenits, Inc., Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111"]},{"raw_affiliation_string":"Texas Instruments Dallas, TX","institution_ids":["https://openalex.org/I74760111"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5032620780"],"corresponding_institution_ids":["https://openalex.org/I126345244"],"apc_list":null,"apc_paid":null,"fwci":1.2593,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.80872387,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reset","display_name":"Reset (finance)","score":0.6609894037246704},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6379068493843079},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.6077402234077454},{"id":"https://openalex.org/keywords/test-method","display_name":"Test method","score":0.46152985095977783},{"id":"https://openalex.org/keywords/sort","display_name":"sort","score":0.4527072310447693},{"id":"https://openalex.org/keywords/test-data","display_name":"Test data","score":0.43639451265335083},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.43155238032341003},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38773220777511597},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3740292191505432},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.35583260655403137},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.3356451392173767},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20168280601501465},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17034944891929626},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.14423158764839172}],"concepts":[{"id":"https://openalex.org/C2779795794","wikidata":"https://www.wikidata.org/wiki/Q7315343","display_name":"Reset (finance)","level":2,"score":0.6609894037246704},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6379068493843079},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.6077402234077454},{"id":"https://openalex.org/C132519959","wikidata":"https://www.wikidata.org/wiki/Q3077373","display_name":"Test method","level":2,"score":0.46152985095977783},{"id":"https://openalex.org/C88548561","wikidata":"https://www.wikidata.org/wiki/Q347599","display_name":"sort","level":2,"score":0.4527072310447693},{"id":"https://openalex.org/C16910744","wikidata":"https://www.wikidata.org/wiki/Q7705759","display_name":"Test data","level":2,"score":0.43639451265335083},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.43155238032341003},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38773220777511597},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3740292191505432},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.35583260655403137},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.3356451392173767},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20168280601501465},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17034944891929626},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.14423158764839172},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C23123220","wikidata":"https://www.wikidata.org/wiki/Q816826","display_name":"Information retrieval","level":1,"score":0.0},{"id":"https://openalex.org/C106159729","wikidata":"https://www.wikidata.org/wiki/Q2294553","display_name":"Financial economics","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2011.6139173","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2011.6139173","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6200000047683716}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1531696936","https://openalex.org/W1601240628","https://openalex.org/W1902239726","https://openalex.org/W1970652057","https://openalex.org/W2020406315","https://openalex.org/W2030446795","https://openalex.org/W2045656233","https://openalex.org/W2072993076","https://openalex.org/W2095306774","https://openalex.org/W2103543101","https://openalex.org/W2109971199","https://openalex.org/W2111265284","https://openalex.org/W2112892895","https://openalex.org/W2148280402","https://openalex.org/W2156955559","https://openalex.org/W2158176397","https://openalex.org/W2159233929","https://openalex.org/W2167232152","https://openalex.org/W2807981689","https://openalex.org/W3148816697","https://openalex.org/W4210462867","https://openalex.org/W4388247078"],"related_works":["https://openalex.org/W1895064253","https://openalex.org/W2035832568","https://openalex.org/W1606802855","https://openalex.org/W3121464923","https://openalex.org/W2170365398","https://openalex.org/W4233031093","https://openalex.org/W2354567518","https://openalex.org/W2475020399","https://openalex.org/W4236395861","https://openalex.org/W2005741104"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"an":[3],"adaptive":[4],"test":[5,10,13,21,62],"method":[6,25],"to":[7,29,73],"dynamically":[8],"control":[9],"flow":[11],"and":[12,40,51],"contents":[14],"with":[15,85],"continuous":[16],"per":[17],"die":[18],"updates":[19],"of":[20,46,80],"fail":[22,33,49],"rates.":[23],"The":[24],"employs":[26],"Bayesian":[27],"statistics":[28,45],"model":[30],"a":[31,56],"separate":[32],"rate":[34],"for":[35,65],"each":[36],"test.":[37],"Test":[38,77],"reordering":[39],"elimination":[41],"is":[42,52,71],"based":[43,58],"on":[44],"these":[47],"predicted":[48],"rates":[50],"naturally":[53],"monitored":[54],"by":[55],"wafer":[57],"reset.":[59],"Wafer":[60],"sort":[61],"response":[63],"data":[64],"two":[66],"65nm":[67],"integrated":[68],"circuit":[69],"products":[70],"used":[72],"demonstrate":[74],"this":[75],"method.":[76],"time":[78],"reductions":[79],"about":[81],"30%":[82],"are":[83],"achieved":[84],"quality":[86],"levels":[87],"within":[88],"industry":[89],"expectations.":[90]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}