{"id":"https://openalex.org/W2029243854","doi":"https://doi.org/10.1109/test.2011.6139172","title":"Techniques to improve memory interface test quality for complex SoCs","display_name":"Techniques to improve memory interface test quality for complex SoCs","publication_year":2011,"publication_date":"2011-09-01","ids":{"openalex":"https://openalex.org/W2029243854","doi":"https://doi.org/10.1109/test.2011.6139172","mag":"2029243854"},"language":"en","primary_location":{"id":"doi:10.1109/test.2011.6139172","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2011.6139172","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028487496","display_name":"V.R. Devanathan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"V. R. Devanathan","raw_affiliation_strings":["Texas Instruments (India) Private Limited, Bangalore, India","Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India"],"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I4210109535"]},{"raw_affiliation_string":"Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India","institution_ids":["https://openalex.org/I4210109535"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045071073","display_name":"Srinivas Vooka","orcid":null},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Srinivas Vooka","raw_affiliation_strings":["Texas Instruments (India) Private Limited, Bangalore, India","Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India"],"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Private Limited, Bangalore, India","institution_ids":["https://openalex.org/I4210109535"]},{"raw_affiliation_string":"Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India","institution_ids":["https://openalex.org/I4210109535"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5028487496"],"corresponding_institution_ids":["https://openalex.org/I4210109535"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.0926792,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.7646666765213013},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7116726040840149},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6762832403182983},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.520275890827179},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.47148749232292175},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.43333783745765686},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3315391540527344},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3281763195991516},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2319018542766571},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1518622636795044},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.08592009544372559},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07775536179542542}],"concepts":[{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.7646666765213013},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7116726040840149},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6762832403182983},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.520275890827179},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.47148749232292175},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.43333783745765686},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3315391540527344},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3281763195991516},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2319018542766571},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1518622636795044},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.08592009544372559},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07775536179542542},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2011.6139172","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2011.6139172","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1485955567","https://openalex.org/W1841500099","https://openalex.org/W2005027393","https://openalex.org/W2058775255","https://openalex.org/W2100483769","https://openalex.org/W2110881494","https://openalex.org/W2120349980","https://openalex.org/W2125545672","https://openalex.org/W2128767249","https://openalex.org/W2141568925","https://openalex.org/W2143192260","https://openalex.org/W2144511081","https://openalex.org/W2146056662","https://openalex.org/W2149602237","https://openalex.org/W2157275977","https://openalex.org/W2177578610","https://openalex.org/W2218792917","https://openalex.org/W3147331103","https://openalex.org/W6628916276","https://openalex.org/W6651620725"],"related_works":["https://openalex.org/W2131559056","https://openalex.org/W4254560580","https://openalex.org/W2127167802","https://openalex.org/W2080984854","https://openalex.org/W2323083271","https://openalex.org/W2019500818","https://openalex.org/W2009690023","https://openalex.org/W2163047760","https://openalex.org/W2955439067","https://openalex.org/W1519923721"],"abstract_inverted_index":{"Aggressive":[0],"speed":[1,120],"and":[2,77],"voltage":[3],"binning":[4,30],"schemes":[5,62],"are":[6,49],"widely":[7],"used":[8,28],"in":[9,36,42],"the":[10,14,26,32,37,51,65,113,116],"industry":[11],"to":[12,63],"improve":[13,64],"yield":[15],"of":[16,67,87,100,115],"SoCs.":[17,89],"For":[18],"accurate":[19],"bin":[20],"classification,":[21],"it":[22],"is":[23],"essential":[24],"that":[25,45],"tests":[27],"for":[29,80,119],"target":[31],"worst":[33],"critical/speed-limiting":[34],"paths":[35,48,86],"design.":[38],"We":[39,72],"have":[40],"observed":[41],"many":[43],"SoCs":[44],"memory":[46,68,102],"interface":[47,69,103],"amongst":[50],"top":[52],"critical":[53],"paths.":[54],"In":[55],"this":[56],"paper,":[57],"we":[58],"propose":[59,78],"new":[60],"DFT":[61],"quality":[66],"logic":[70],"test.":[71],"also":[73],"discuss":[74],"practical":[75],"challenges":[76],"solutions":[79],"successfully":[81],"implementing":[82],"ATPG":[83],"on":[84,92],"memory-interface":[85],"large":[88],"Experimental":[90],"results":[91],"40nm":[93],"industrial":[94],"designs":[95],"show":[96],"an":[97],"average":[98],"increase":[99],"36%":[101],"fault":[104],"coverage.":[105],"Fmax":[106],"result":[107],"from":[108],"production":[109],"SoC":[110],"silicon":[111],"establishes":[112],"effectiveness":[114],"proposed":[117],"scheme":[118],"binning.":[121]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}