{"id":"https://openalex.org/W2087726305","doi":"https://doi.org/10.1109/test.2011.6139166","title":"Hardware hooks for transition scan characterization","display_name":"Hardware hooks for transition scan characterization","publication_year":2011,"publication_date":"2011-09-01","ids":{"openalex":"https://openalex.org/W2087726305","doi":"https://doi.org/10.1109/test.2011.6139166","mag":"2087726305"},"language":"en","primary_location":{"id":"doi:10.1109/test.2011.6139166","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2011.6139166","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015375859","display_name":"P. Pant","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Pankaj Pant","raw_affiliation_strings":["Intel Corporation, Hudson, MA, USA","Intel Corporation, 75 Reed Road, Hudson, MA 01749"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hudson, MA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, 75 Reed Road, Hudson, MA 01749","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073484192","display_name":"Eric Skeels","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eric Skeels","raw_affiliation_strings":["Intel Corporation, Hudson, MA, USA","Intel Corporation, 75 Reed Road, Hudson, MA 01749"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hudson, MA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, 75 Reed Road, Hudson, MA 01749","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5015375859"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.5112,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.83611721,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"3","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6168943643569946},{"id":"https://openalex.org/keywords/software-deployment","display_name":"Software deployment","score":0.5721396803855896},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.4899412989616394},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.42013856768608093},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3898688554763794},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31572961807250977}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6168943643569946},{"id":"https://openalex.org/C105339364","wikidata":"https://www.wikidata.org/wiki/Q2297740","display_name":"Software deployment","level":2,"score":0.5721396803855896},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.4899412989616394},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.42013856768608093},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3898688554763794},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31572961807250977}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2011.6139166","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2011.6139166","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1568407911","https://openalex.org/W2004437077","https://openalex.org/W2056941659","https://openalex.org/W2066421651","https://openalex.org/W2111531873","https://openalex.org/W2111944961","https://openalex.org/W2121975281","https://openalex.org/W2139642492","https://openalex.org/W2151740582","https://openalex.org/W2153171864","https://openalex.org/W2164754947","https://openalex.org/W6651354974"],"related_works":["https://openalex.org/W2770234245","https://openalex.org/W96612179","https://openalex.org/W4229499248","https://openalex.org/W2566006169","https://openalex.org/W1567818861","https://openalex.org/W2987774938","https://openalex.org/W4256492088","https://openalex.org/W1987313229","https://openalex.org/W2001393705","https://openalex.org/W2357771869"],"abstract_inverted_index":{"Comprehensive":[0],"transition":[1],"scan":[2,35,93],"content":[3],"was":[4,30],"deployed":[5,77],"on":[6,44],"an":[7,45],"Intel":[8,46],"<sup":[9,13,47],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[10,14,48],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\u00ae</sup>":[11,15,49],"Itanium":[12],"server":[16],"microprocessor":[17],"design,":[18,52],"including":[19],"full":[20],"coverage":[21],"patterns":[22,36],"for":[23],"all":[24,61],"core":[25,51],"logic":[26],"blocks.":[27],"Since":[28],"this":[29,105],"the":[31,53,81,85,91],"first":[32],"time":[33],"at-speed":[34,92],"were":[37,66,76],"being":[38],"planned":[39],"as":[40],"a":[41],"manufacturing":[42],"screen":[43],"CPU":[50],"test":[54],"deployment":[55],"team":[56,83],"needed":[57],"to":[58,78,88],"ensure":[59,79],"that":[60,80,101],"concerns":[62],"of":[63],"over-and":[64],"under-testing":[65],"systematically":[67],"addressed.":[68],"A":[69],"few":[70],"innovative":[71],"and":[72],"novel":[73],"DFT":[74,99],"solutions":[75,100],"post-silicon":[82],"had":[84],"adequate":[86],"tools":[87],"fully":[89],"analyze":[90],"content.":[94],"This":[95],"paper":[96],"describes":[97],"these":[98],"proved":[102],"invaluable":[103],"during":[104],"process.":[106]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}