{"id":"https://openalex.org/W1975544287","doi":"https://doi.org/10.1109/test.2010.5699295","title":"A novel approach to improve test coverage of BSR cells","display_name":"A novel approach to improve test coverage of BSR cells","publication_year":2010,"publication_date":"2010-11-01","ids":{"openalex":"https://openalex.org/W1975544287","doi":"https://doi.org/10.1109/test.2010.5699295","mag":"1975544287"},"language":"en","primary_location":{"id":"doi:10.1109/test.2010.5699295","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2010.5699295","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045026834","display_name":"Ankush Srivastava","orcid":"https://orcid.org/0000-0002-7894-3952"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Ankush Srivastava","raw_affiliation_strings":["Freescale Semiconductor, Inc., Noida, India","Freescale Semiconductor Inc., Noida, India#TAB#"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., Noida, India","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor Inc., Noida, India#TAB#","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102307646","display_name":"Ajay Kumar Prajapati","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ajay Prajapati","raw_affiliation_strings":["Freescale Semiconductor, Inc., Noida, India","Freescale Semiconductor Inc., Noida, India#TAB#"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., Noida, India","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor Inc., Noida, India#TAB#","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002534580","display_name":"Vinay Soni","orcid":"https://orcid.org/0000-0003-2401-6165"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Vinay Soni","raw_affiliation_strings":["Freescale Semiconductor, Inc., Noida, India","Freescale Semiconductor Inc., Noida, India#TAB#"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Inc., Noida, India","institution_ids":[]},{"raw_affiliation_string":"Freescale Semiconductor Inc., Noida, India#TAB#","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5045026834"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9987,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.7645755,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9936000108718872,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.7644380331039429},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6723718047142029},{"id":"https://openalex.org/keywords/code-coverage","display_name":"Code coverage","score":0.5974996089935303},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5877318978309631},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.5802876949310303},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5757787823677063},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.5644145607948303},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5603466033935547},{"id":"https://openalex.org/keywords/boundary-scan","display_name":"Boundary scan","score":0.5593501925468445},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.5245504379272461},{"id":"https://openalex.org/keywords/test-plan","display_name":"Test plan","score":0.4853619337081909},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.4610551595687866},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4423021972179413},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36770209670066833},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.31226104497909546},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.20041048526763916},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17836129665374756},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.16966378688812256},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.16373902559280396},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13916438817977905}],"concepts":[{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.7644380331039429},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6723718047142029},{"id":"https://openalex.org/C53942775","wikidata":"https://www.wikidata.org/wiki/Q1211721","display_name":"Code coverage","level":3,"score":0.5974996089935303},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5877318978309631},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.5802876949310303},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5757787823677063},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.5644145607948303},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5603466033935547},{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.5593501925468445},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.5245504379272461},{"id":"https://openalex.org/C12148698","wikidata":"https://www.wikidata.org/wiki/Q364651","display_name":"Test plan","level":3,"score":0.4853619337081909},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.4610551595687866},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4423021972179413},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36770209670066833},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31226104497909546},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.20041048526763916},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17836129665374756},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.16966378688812256},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.16373902559280396},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13916438817977905},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C2776746162","wikidata":"https://www.wikidata.org/wiki/Q4508","display_name":"Navy","level":2,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2010.5699295","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2010.5699295","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5799999833106995,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2028504835","https://openalex.org/W4231486519"],"related_works":["https://openalex.org/W2117171289","https://openalex.org/W2102314186","https://openalex.org/W256629098","https://openalex.org/W2233209732","https://openalex.org/W2105797754","https://openalex.org/W2127184179","https://openalex.org/W4254647022","https://openalex.org/W1592537894","https://openalex.org/W2128260177","https://openalex.org/W2163124097"],"abstract_inverted_index":{"In":[0],"Today's":[1],"competitive":[2],"and":[3,10,47,69,122,152],"rapidly":[4],"changing":[5],"electronics":[6],"market,":[7],"the":[8,36,44,55,74,104,113,124,130,145,148,171,187],"speed":[9],"effectiveness":[11],"of":[12,30,42,76,94,108,147,186],"product":[13],"testing":[14],"have":[15],"a":[16,39,85,92],"significant":[17],"impact":[18],"on":[19,164],"time-to-market.":[20],"You":[21],"need":[22,37],"to":[23,49,72,102,138,158,170,174,184,193],"make":[24],"Design-For-Testability":[25],"(DFT)":[26],"an":[27],"essential":[28],"part":[29,93],"your":[31],"design":[32,179],"process,":[33],"along":[34],"with":[35,167],"for":[38],"reliable":[40],"method":[41],"knowing":[43],"test":[45,87],"coverage":[46,107],"how":[48],"improve":[50],"it.":[51],"This":[52,143,176],"paper":[53],"describes":[54],"modified":[56],"Boundary-Scan":[57,70,197],"Register":[58],"(BSR)":[59],"Cell,":[60],"described":[61],"in":[62,80,119,129],"IEEE":[63,194],"1149.1":[64,196],"Standard":[65,195],"Test":[66],"Access":[67],"Port":[68],"Architecture,":[71],"facilitate":[73],"detection":[75],"additional":[77],"manufacturing":[78,136],"defects":[79,137],"BSR":[81,96,109,120,141,149,177],"Cell":[82],"by":[83,111],"adding":[84],"small":[86],"logic,":[88],"which":[89],"will":[90,153],"become":[91],"original":[95],"Cell.":[97],"The":[98],"basic":[99],"idea":[100],"is":[101,126],"increase":[103],"stuck-at":[105],"fault":[106],"cell":[110,178,190],"including":[112],"update-register":[114,125],"(latched":[115],"parallel":[116],"output)":[117],"Flip-Flop":[118],"chain":[121],"once":[123],"being":[127],"included":[128],"chain;":[131],"we":[132],"can":[133,181],"target":[134],"more":[135],"cover":[139],"during":[140],"chain-test.":[142],"increases":[144],"fault-coverage":[146],"Pad":[150],"Ring":[151],"also":[154],"help":[155],"validation":[156],"engineers":[157],"ease":[159],"out":[160],"their":[161],"debugging":[162],"efforts":[163],"board":[165],"level":[166],"added":[168],"quality":[169],"delivered":[172],"chips":[173],"customer.":[175],"modification":[180],"be":[182],"extended":[183],"any":[185],"BC":[188],"type":[189],"structure,":[191],"compliant":[192],"Architecture.":[198]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}