{"id":"https://openalex.org/W2157212570","doi":"https://doi.org/10.1109/test.2010.5699265","title":"Constrained ATPG for functional RTL circuits using F-Scan","display_name":"Constrained ATPG for functional RTL circuits using F-Scan","publication_year":2010,"publication_date":"2010-11-01","ids":{"openalex":"https://openalex.org/W2157212570","doi":"https://doi.org/10.1109/test.2010.5699265","mag":"2157212570"},"language":"en","primary_location":{"id":"doi:10.1109/test.2010.5699265","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2010.5699265","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056654865","display_name":"Marie Engelene J. Obien","orcid":"https://orcid.org/0000-0002-7169-3292"},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Marie Engelene J. Obien","raw_affiliation_strings":["Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan","institution_ids":["https://openalex.org/I75917431"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022717526","display_name":"Satoshi Ohtake","orcid":null},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Satoshi Ohtake","raw_affiliation_strings":["Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan","institution_ids":["https://openalex.org/I75917431"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111955990","display_name":"Hideo Fujiwara","orcid":null},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hideo Fujiwara","raw_affiliation_strings":["Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan","institution_ids":["https://openalex.org/I75917431"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7591,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.7517658,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"13","issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.9422345161437988},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.7715311646461487},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.6585615873336792},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6574392318725586},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5917674899101257},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.5760326981544495},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.5293555855751038},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.5240652561187744},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4847533404827118},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4727255702018738},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4623490571975708},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.4545111656188965},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4525824785232544},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.44303297996520996},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4055655300617218},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3844146430492401},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.36606043577194214},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36489468812942505},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.34510743618011475},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16687369346618652},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.1260075867176056}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.9422345161437988},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.7715311646461487},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.6585615873336792},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6574392318725586},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5917674899101257},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.5760326981544495},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5293555855751038},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.5240652561187744},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4847533404827118},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4727255702018738},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4623490571975708},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.4545111656188965},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4525824785232544},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.44303297996520996},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4055655300617218},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3844146430492401},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.36606043577194214},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36489468812942505},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.34510743618011475},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16687369346618652},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.1260075867176056},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2010.5699265","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2010.5699265","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1572946573","https://openalex.org/W1837475237","https://openalex.org/W1852311849","https://openalex.org/W1855007419","https://openalex.org/W1863116566","https://openalex.org/W1997565760","https://openalex.org/W2001642815","https://openalex.org/W2038133068","https://openalex.org/W2054781056","https://openalex.org/W2071376191","https://openalex.org/W2078888330","https://openalex.org/W2107772923","https://openalex.org/W2110578688","https://openalex.org/W2114866327","https://openalex.org/W2115180022","https://openalex.org/W2118623093","https://openalex.org/W2118744758","https://openalex.org/W2124618076","https://openalex.org/W2127323744","https://openalex.org/W2128229078","https://openalex.org/W2129428181","https://openalex.org/W2133745968","https://openalex.org/W2146657836","https://openalex.org/W2150670853","https://openalex.org/W2152476646","https://openalex.org/W2160753176","https://openalex.org/W2166251879","https://openalex.org/W2170923027","https://openalex.org/W2294133975","https://openalex.org/W3148315526","https://openalex.org/W4253755996","https://openalex.org/W4302084786","https://openalex.org/W6649619077","https://openalex.org/W6677183569","https://openalex.org/W6682516163","https://openalex.org/W6696724158"],"related_works":["https://openalex.org/W1581610324","https://openalex.org/W2129124567","https://openalex.org/W2056440717","https://openalex.org/W4231097844","https://openalex.org/W2167571917","https://openalex.org/W3088373974","https://openalex.org/W2620614665","https://openalex.org/W2146547687","https://openalex.org/W2157212570","https://openalex.org/W1595513435"],"abstract_inverted_index":{"In":[0],"this":[1,95],"paper,":[2],"we":[3,73],"present":[4],"an":[5],"approach":[6],"to":[7,51,102],"constrained":[8],"automatic":[9],"test":[10,77,86,100,109],"pattern":[11],"generation":[12,78],"(ATPG)":[13],"for":[14,41],"functional":[15,37],"circuits":[16],"at":[17,69,114],"register-transfer":[18],"level":[19],"(RTL)":[20],"with":[21,121],"the":[22,47,61,75,81,85,90,98,103,115,122,132],"help":[23],"of":[24,80,92,119,124],"a":[25],"design-for-testability":[26],"(DFT)":[27],"technique":[28],"called":[29],"F-scan.":[30],"The":[31,117],"DFT":[32],"method":[33],"optimally":[34],"utilizes":[35],"existing":[36],"elements":[38],"and":[39,65,108],"paths":[40],"test,":[42],"thus":[43],"it":[44],"effectively":[45],"reduces":[46],"hardware":[48],"overhead":[49],"due":[50],"test.":[52],"This":[53],"is":[54,112,129],"done":[55],"by":[56],"arranging":[57],"all":[58],"registers":[59],"in":[60],"circuit":[62,82],"into":[63],"F-scan-paths":[64,104],"augmenting":[66],"necessary":[67],"circuitry":[68],"RTL.":[70],"After":[71],"DFT,":[72],"create":[74],"constraint":[76],"model":[79],"based":[83],"on":[84],"environment":[87],"obtained":[88],"from":[89],"information":[91],"F-scan-paths.":[93],"With":[94],"approach,":[96],"only":[97],"applicable":[99],"vectors":[101],"can":[105],"be":[106],"generated":[107],"application":[110],"time":[111],"kept":[113],"minimum.":[116],"comparison":[118],"F-scan":[120],"performance":[123],"gate-level":[125],"full":[126],"scan":[127],"design":[128],"shown":[130],"through":[131],"experimental":[133],"results.":[134]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}