{"id":"https://openalex.org/W2144511081","doi":"https://doi.org/10.1109/test.2010.5699212","title":"Towards effective and compression-friendly test of memory interface logic","display_name":"Towards effective and compression-friendly test of memory interface logic","publication_year":2010,"publication_date":"2010-11-01","ids":{"openalex":"https://openalex.org/W2144511081","doi":"https://doi.org/10.1109/test.2010.5699212","mag":"2144511081"},"language":"en","primary_location":{"id":"doi:10.1109/test.2010.5699212","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2010.5699212","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028487496","display_name":"V.R. Devanathan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"V.R. Devanathan","raw_affiliation_strings":["Texas Instruments (India) Pvt. Ltd., Bangalore, India","Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India"],"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Pvt. Ltd., Bangalore, India","institution_ids":["https://openalex.org/I4210109535"]},{"raw_affiliation_string":"Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India","institution_ids":["https://openalex.org/I4210109535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091430006","display_name":"Alan Hales","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alan Hales","raw_affiliation_strings":["Texas Instruments Inc., Dallas, TX, USA","Texas Instruments Inc., Dallas, 75266, USA"],"affiliations":[{"raw_affiliation_string":"Texas Instruments Inc., Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111"]},{"raw_affiliation_string":"Texas Instruments Inc., Dallas, 75266, USA","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039259992","display_name":"Sumant Kale","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sumant Kale","raw_affiliation_strings":["Texas Instruments Inc., Dallas, TX, USA","Texas Instruments Inc., Dallas, 75266, USA"],"affiliations":[{"raw_affiliation_string":"Texas Instruments Inc., Dallas, TX, USA","institution_ids":["https://openalex.org/I74760111"]},{"raw_affiliation_string":"Texas Instruments Inc., Dallas, 75266, USA","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012856001","display_name":"Dharmesh Sonkar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Dharmesh Sonkar","raw_affiliation_strings":["Texas Instruments (India) Pvt. Ltd., Bangalore, India","Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India"],"affiliations":[{"raw_affiliation_string":"Texas Instruments (India) Pvt. Ltd., Bangalore, India","institution_ids":["https://openalex.org/I4210109535"]},{"raw_affiliation_string":"Texas Instruments (India) Pvt. Ltd., Bangalore 560093, India","institution_ids":["https://openalex.org/I4210109535"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5028487496"],"corresponding_institution_ids":["https://openalex.org/I4210109535"],"apc_list":null,"apc_paid":null,"fwci":0.4994,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.68478366,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7519059777259827},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6699395179748535},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6118391156196594},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5413543581962585},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5073713660240173},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.499906063079834},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48804986476898193},{"id":"https://openalex.org/keywords/compression","display_name":"Compression (physics)","score":0.46303045749664307},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3532678484916687},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3510446548461914},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3378027081489563},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12072023749351501},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0914478600025177}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7519059777259827},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6699395179748535},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6118391156196594},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5413543581962585},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5073713660240173},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.499906063079834},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48804986476898193},{"id":"https://openalex.org/C180016635","wikidata":"https://www.wikidata.org/wiki/Q2712821","display_name":"Compression (physics)","level":2,"score":0.46303045749664307},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3532678484916687},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3510446548461914},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3378027081489563},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12072023749351501},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0914478600025177},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2010.5699212","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2010.5699212","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4099999964237213,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1581327216","https://openalex.org/W1841500099","https://openalex.org/W1874075800","https://openalex.org/W2005027393","https://openalex.org/W2058775255","https://openalex.org/W2117648153","https://openalex.org/W2120349980","https://openalex.org/W2143192260","https://openalex.org/W2146056662","https://openalex.org/W2152506767","https://openalex.org/W2167253897","https://openalex.org/W3147331103","https://openalex.org/W6651620725"],"related_works":["https://openalex.org/W2116677773","https://openalex.org/W2165367082","https://openalex.org/W2131559056","https://openalex.org/W4254560580","https://openalex.org/W2127167802","https://openalex.org/W2155261584","https://openalex.org/W2163047760","https://openalex.org/W2955439067","https://openalex.org/W1519923721","https://openalex.org/W3147676363"],"abstract_inverted_index":{"Cost":[0],"and":[1,69,101],"time-to-market":[2],"considerations":[3],"are":[4,46,72,123],"strongly":[5],"driving":[6],"the":[7,11,26,43,59,82,85,107],"need":[8],"to":[9,57,113],"improve":[10,58],"effectiveness":[12,60,83],"of":[13,28,61,84,115,130],"structural":[14],"patterns":[15,63],"for":[16,33,64],"speed/voltage":[17],"binning.":[18],"In":[19],"this":[20],"paper":[21],"we":[22],"focus":[23],"on":[24,76],"improving":[25],"quality":[27],"testing":[29],"memory":[30,44,54],"interface":[31],"paths":[32],"speed/voltage-binning.":[34],"We":[35,51],"propose":[36,53],"DFT":[37],"schemes":[38,87,122],"that":[39,45,104,114,129],"propagate":[40],"faults":[41],"through":[42],"effective":[47],"with":[48,88],"test":[49,89],"compression.":[50,90],"also":[52,99],"architectural":[55],"enhancements":[56],"ATPG":[62],"Fmax":[65,105,119],"identification.":[66],"Both":[67],"synchronous":[68],"asynchronous":[70],"memories":[71],"targeted.":[73],"Experimental":[74],"results":[75,93],"an":[77],"industrial":[78],"ASIC":[79],"core":[80],"show":[81],"proposed":[86,108],"Initial":[91],"silicon":[92],"from":[94],"a":[95],"40-nm":[96],"testchip":[97],"is":[98,110],"presented":[100],"it":[102],"proves":[103],"using":[106,120],"scheme":[109],"very":[111],"close":[112],"functional":[116,131],"patterns,":[117],"while":[118],"conventional":[121],"more":[124],"than":[125,128],"2X":[126],"higher":[127],"patterns.":[132]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
