{"id":"https://openalex.org/W2075437288","doi":"https://doi.org/10.1109/test.2008.4700629","title":"IEEE 1500 Core Wrapper Optimization Techniques and Implementation","display_name":"IEEE 1500 Core Wrapper Optimization Techniques and Implementation","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2075437288","doi":"https://doi.org/10.1109/test.2008.4700629","mag":"2075437288"},"language":"en","primary_location":{"id":"doi:10.1109/test.2008.4700629","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2008.4700629","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037035551","display_name":"Brendan Mullane","orcid":"https://orcid.org/0000-0003-3764-3555"},"institutions":[{"id":"https://openalex.org/I230495080","display_name":"University of Limerick","ror":"https://ror.org/00a0n9e72","country_code":"IE","type":"education","lineage":["https://openalex.org/I230495080"]}],"countries":["IE"],"is_corresponding":true,"raw_author_name":"B. Mullane","raw_affiliation_strings":["Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland","Dept. of Electron. & Comput. Eng., Univ. of limerick, Limerick"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland","institution_ids":["https://openalex.org/I230495080"]},{"raw_affiliation_string":"Dept. of Electron. & Comput. Eng., Univ. of limerick, Limerick","institution_ids":["https://openalex.org/I230495080"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110206531","display_name":"Michael S. Higgins","orcid":null},"institutions":[{"id":"https://openalex.org/I230495080","display_name":"University of Limerick","ror":"https://ror.org/00a0n9e72","country_code":"IE","type":"education","lineage":["https://openalex.org/I230495080"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"M. Higgins","raw_affiliation_strings":["University of Limerick, Limerick, IE","Dept. of Electron. & Comput. Eng., Univ. of limerick, Limerick"],"affiliations":[{"raw_affiliation_string":"University of Limerick, Limerick, IE","institution_ids":["https://openalex.org/I230495080"]},{"raw_affiliation_string":"Dept. of Electron. & Comput. Eng., Univ. of limerick, Limerick","institution_ids":["https://openalex.org/I230495080"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073044237","display_name":"Ciaran MacNamee","orcid":"https://orcid.org/0000-0002-9066-0971"},"institutions":[{"id":"https://openalex.org/I230495080","display_name":"University of Limerick","ror":"https://ror.org/00a0n9e72","country_code":"IE","type":"education","lineage":["https://openalex.org/I230495080"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"C. MacNamee","raw_affiliation_strings":["University of Limerick, Limerick, IE","Dept. of Electron. & Comput. Eng., Univ. of limerick, Limerick"],"affiliations":[{"raw_affiliation_string":"University of Limerick, Limerick, IE","institution_ids":["https://openalex.org/I230495080"]},{"raw_affiliation_string":"Dept. of Electron. & Comput. Eng., Univ. of limerick, Limerick","institution_ids":["https://openalex.org/I230495080"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5037035551"],"corresponding_institution_ids":["https://openalex.org/I230495080"],"apc_list":null,"apc_paid":null,"fwci":0.6932,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.75296042,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"35","issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7010647058486938},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6995609998703003},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.637903094291687},{"id":"https://openalex.org/keywords/test-vector","display_name":"Test vector","score":0.5077841877937317},{"id":"https://openalex.org/keywords/mode","display_name":"Mode (computer interface)","score":0.46953949332237244},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44630783796310425},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4236873984336853},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.41869112849235535},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.116495281457901},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07234203815460205},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.061270296573638916}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7010647058486938},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6995609998703003},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.637903094291687},{"id":"https://openalex.org/C100767440","wikidata":"https://www.wikidata.org/wiki/Q7705816","display_name":"Test vector","level":3,"score":0.5077841877937317},{"id":"https://openalex.org/C48677424","wikidata":"https://www.wikidata.org/wiki/Q6888088","display_name":"Mode (computer interface)","level":2,"score":0.46953949332237244},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44630783796310425},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4236873984336853},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.41869112849235535},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.116495281457901},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07234203815460205},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.061270296573638916},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2008.4700629","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2008.4700629","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320862","display_name":"University of Limerick","ror":"https://ror.org/00a0n9e72"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W25195582","https://openalex.org/W50600096","https://openalex.org/W1596724070","https://openalex.org/W1924406256","https://openalex.org/W2094067221","https://openalex.org/W2100663632","https://openalex.org/W2125811894","https://openalex.org/W2140432262","https://openalex.org/W2155288938","https://openalex.org/W2155685366","https://openalex.org/W2165642910","https://openalex.org/W2169664457","https://openalex.org/W2499565042","https://openalex.org/W2936804578","https://openalex.org/W6602017653"],"related_works":["https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2913952975","https://openalex.org/W2545901417","https://openalex.org/W2624257274","https://openalex.org/W2549755772","https://openalex.org/W1980697206","https://openalex.org/W2125609625","https://openalex.org/W4241515474"],"abstract_inverted_index":{"IEEE":[0],"1500":[1],"core":[2],"wrappers":[3],"supporting":[4],"a":[5],"hybrid":[6],"scan":[7],"mode":[8],"provide":[9],"for":[10],"lower":[11],"test":[12],"times":[13],"with":[14,29],"minimal":[15],"wiring":[16],"and":[17,22],"logic":[18,21],"overheads.":[19],"Wrapper":[20],"vector":[23],"formats":[24],"that":[25],"are":[26,34],"easily":[27],"integrated":[28],"modern":[30],"IC/FPGA":[31],"design":[32],"flows":[33],"demonstrated.":[35]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
