{"id":"https://openalex.org/W2080816816","doi":"https://doi.org/10.1109/test.2008.4700611","title":"Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits","display_name":"Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2080816816","doi":"https://doi.org/10.1109/test.2008.4700611","mag":"2080816816"},"language":"en","primary_location":{"id":"doi:10.1109/test.2008.4700611","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2008.4700611","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110198364","display_name":"Waleed K. Al-Assadi","orcid":null},"institutions":[{"id":"https://openalex.org/I20382870","display_name":"Missouri University of Science and Technology","ror":"https://ror.org/00scwqd12","country_code":"US","type":"education","lineage":["https://openalex.org/I20382870"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"W.K. Al-Assadi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Missouri University of Science and Technology, Rolla, MO, USA","Dept. of Electr. & Comput. Eng., Missouri Univ. of Sci. & Technol., Rolla, MO#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Missouri University of Science and Technology, Rolla, MO, USA","institution_ids":["https://openalex.org/I20382870"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Missouri Univ. of Sci. & Technol., Rolla, MO#TAB#","institution_ids":["https://openalex.org/I20382870"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068271464","display_name":"Sindhu Kakarla","orcid":null},"institutions":[{"id":"https://openalex.org/I20382870","display_name":"Missouri University of Science and Technology","ror":"https://ror.org/00scwqd12","country_code":"US","type":"education","lineage":["https://openalex.org/I20382870"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Kakarla","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Missouri University of Science and Technology, Rolla, MO, USA","Dept. of Electr. & Comput. Eng., Missouri Univ. of Sci. & Technol., Rolla, MO#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Missouri University of Science and Technology, Rolla, MO, USA","institution_ids":["https://openalex.org/I20382870"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Missouri Univ. of Sci. & Technol., Rolla, MO#TAB#","institution_ids":["https://openalex.org/I20382870"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5110198364"],"corresponding_institution_ids":["https://openalex.org/I20382870"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.07852914,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"9"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.7560672760009766},{"id":"https://openalex.org/keywords/observability","display_name":"Observability","score":0.7067502737045288},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.6700010299682617},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6397725343704224},{"id":"https://openalex.org/keywords/controllability","display_name":"Controllability","score":0.6312993168830872},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6107876896858215},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5900084376335144},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5273830890655518},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4953685998916626},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45692184567451477},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4389096796512604},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.42979228496551514},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.41363003849983215},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3999423384666443},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38276851177215576},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2326716184616089},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.1937147080898285},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14835307002067566},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.13347786664962769}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.7560672760009766},{"id":"https://openalex.org/C36299963","wikidata":"https://www.wikidata.org/wiki/Q1369844","display_name":"Observability","level":2,"score":0.7067502737045288},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.6700010299682617},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6397725343704224},{"id":"https://openalex.org/C48209547","wikidata":"https://www.wikidata.org/wiki/Q1331104","display_name":"Controllability","level":2,"score":0.6312993168830872},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6107876896858215},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5900084376335144},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5273830890655518},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4953685998916626},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45692184567451477},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4389096796512604},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.42979228496551514},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.41363003849983215},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3999423384666443},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38276851177215576},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2326716184616089},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.1937147080898285},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14835307002067566},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.13347786664962769},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2008.4700611","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2008.4700611","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W189036309","https://openalex.org/W1595368737","https://openalex.org/W1950529005","https://openalex.org/W1992723344","https://openalex.org/W2023686814","https://openalex.org/W2085697604","https://openalex.org/W2098326421","https://openalex.org/W2109020844","https://openalex.org/W2110967082","https://openalex.org/W2117299791","https://openalex.org/W2124714593","https://openalex.org/W2127709476","https://openalex.org/W2130530168","https://openalex.org/W2159042429","https://openalex.org/W2295534994","https://openalex.org/W2911717499","https://openalex.org/W4231670955","https://openalex.org/W6678604216"],"related_works":["https://openalex.org/W2543176856","https://openalex.org/W2117873690","https://openalex.org/W3141249762","https://openalex.org/W2137555930","https://openalex.org/W1679970298","https://openalex.org/W2624668974","https://openalex.org/W2140497172","https://openalex.org/W2157154381","https://openalex.org/W4253743993","https://openalex.org/W2166402441"],"abstract_inverted_index":{"Due":[0],"to":[1,33,37,91],"the":[2,9,18,93],"absence":[3],"of":[4,11,95],"a":[5,44,51,115],"global":[6],"clock":[7],"and":[8,20,87,98,114],"presence":[10],"more":[12],"state":[13],"holding":[14],"elements":[15],"that":[16,103],"synchronize":[17],"control":[19],"data":[21],"paths,":[22],"conventional":[23],"Automatic":[24,108],"Test":[25],"Pattern":[26],"Generation":[27],"(ATPG)":[28],"algorithms":[29],"fail":[30],"when":[31],"applied":[32],"asynchronous":[34,53],"circuits,":[35],"leading":[36],"poor":[38],"fault":[39,101],"coverage.":[40],"This":[41],"paper":[42],"presents":[43],"design":[45,54],"for":[46,50,100],"test":[47,79],"(DFT)":[48],"technique":[49,77,127],"popular":[52],"paradigm":[55],"called":[56],"NULL":[57],"Convention":[58],"Logic":[59],"(NCL)":[60],"aimed":[61],"at":[62],"making":[63],"NCL":[64,118,133],"designs":[65],"testable":[66],"using":[67,83],"existing":[68],"DFT":[69,109,126],"tools":[70],"with":[71],"reasonable":[72],"gate":[73],"overhead.":[74],"The":[75,124],"proposed":[76],"performs":[78],"points":[80],"(TPs)":[81],"insertion":[82],"SCOAP":[84],"(Sandia":[85],"Controllability":[86],"Observability":[88],"Program)":[89],"analysis":[90],"enhance":[92],"controllability":[94],"feedback":[96],"nets":[97],"observability":[99],"sites":[102],"are":[104,122],"flagged":[105],"unobservable.":[106],"An":[107],"Insertion":[110],"Flow":[111],"(ADIF)":[112],"algorithm":[113],"custom":[116],"ATPG":[117],"primitive":[119],"gates":[120],"library":[121],"developed.":[123],"developed":[125],"has":[128],"been":[129],"verified":[130],"on":[131],"several":[132],"benchmark":[134],"circuits.":[135]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}