{"id":"https://openalex.org/W1995848150","doi":"https://doi.org/10.1109/test.2007.4437657","title":"JTAG system test in a MicroTCA world","display_name":"JTAG system test in a MicroTCA world","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W1995848150","doi":"https://doi.org/10.1109/test.2007.4437657","mag":"1995848150"},"language":"en","primary_location":{"id":"doi:10.1109/test.2007.4437657","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2007.4437657","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001743076","display_name":"Bradford G. Van Treuren","orcid":null},"institutions":[{"id":"https://openalex.org/I1322087612","display_name":"Alcatel Lucent (Germany)","ror":"https://ror.org/00c5mwp75","country_code":"DE","type":"company","lineage":["https://openalex.org/I1322087612"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Bradford G. Van Treuren","raw_affiliation_strings":["Alcatel-Lucent, Murray Hill, NJ, USA","[Alcatel-Lucent, Murray Hill, NJ]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Alcatel-Lucent, Murray Hill, NJ, USA","institution_ids":[]},{"raw_affiliation_string":"[Alcatel-Lucent, Murray Hill, NJ]","institution_ids":["https://openalex.org/I1322087612"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110221850","display_name":"Adam W Ley","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Adam Ley","raw_affiliation_strings":["ASSET InterTech, Inc., Richardson, TX, USA","ASSET InterTech, Inc., Richardson, Texas, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ASSET InterTech, Inc., Richardson, TX, USA","institution_ids":[]},{"raw_affiliation_string":"ASSET InterTech, Inc., Richardson, Texas, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3184,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.61461222,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.808151364326477},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7189853191375732},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5883796811103821},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5198457837104797},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5046998262405396},{"id":"https://openalex.org/keywords/system-testing","display_name":"System testing","score":0.42097288370132446},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3933347463607788},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.34601736068725586},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.32994896173477173},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.17779651284217834},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.16216027736663818}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.808151364326477},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7189853191375732},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5883796811103821},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5198457837104797},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5046998262405396},{"id":"https://openalex.org/C7166840","wikidata":"https://www.wikidata.org/wiki/Q1199682","display_name":"System testing","level":2,"score":0.42097288370132446},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3933347463607788},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.34601736068725586},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.32994896173477173},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.17779651284217834},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.16216027736663818},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2007.4437657","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2007.4437657","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6100000143051147,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2109154609","https://openalex.org/W2135743693","https://openalex.org/W2146443411","https://openalex.org/W2165036962","https://openalex.org/W2187203472","https://openalex.org/W6687195677"],"related_works":["https://openalex.org/W2393524141","https://openalex.org/W2365130684","https://openalex.org/W2370255574","https://openalex.org/W2169676947","https://openalex.org/W2906367154","https://openalex.org/W1979652744","https://openalex.org/W2158769803","https://openalex.org/W2360820851","https://openalex.org/W2154035833","https://openalex.org/W2107904603"],"abstract_inverted_index":{"The":[0],"telecommunications":[1],"industry":[2],"has":[3],"developed":[4],"new":[5],"system":[6,62],"architectures":[7],"through":[8],"the":[9,19,29,41,61,67,72,79,87,106],"PCI":[10],"Industrial":[11],"Computer":[12],"Manufacturers":[13],"Group":[14],"(PICMG)":[15],"organization.":[16],"These":[17],"are":[18],"Advanced":[20,32],"Telecom":[21],"Computing":[22],"Architecture":[23],"(ATCA)":[24],"platforms":[25],"that":[26,99],"consist":[27],"of":[28],"ATCA,":[30],"ATCA300,":[31],"Mezzanine":[33],"Card":[34],"(AMC),":[35],"and":[36,43],"MicroTCA":[37,44,68,80],"specifications.":[38],"Unfortunately,":[39],"only":[40],"AMC":[42,74,89],"specification":[45,69],"directly":[46],"addresses":[47],"testability":[48],"using":[49,94],"an":[50],"IEEE":[51],"Std":[52],"1149.1":[53],"(JTAG)":[54],"compatible":[55],"interface.":[56],"This":[57],"paper":[58],"will":[59],"address":[60],"test":[63],"facility":[64],"specified":[65],"in":[66,105],"for":[70],"testing":[71],"incorporated":[73],"modules":[75],"as":[76,78],"well":[77],"Carrier":[81],"Hub":[82],"(MCH)":[83],"controllers.":[84],"Access":[85],"to":[86],"individual":[88],"JTAG":[90,96],"chains":[91],"is":[92],"provided":[93],"a":[95,101],"Switch":[97],"Module":[98],"provides":[100],"programmable":[102],"star":[103],"architecture":[104],"system.":[107]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}