{"id":"https://openalex.org/W2153973228","doi":"https://doi.org/10.1109/test.2007.4437656","title":"IJTAG: The path to organized instrument connectivity","display_name":"IJTAG: The path to organized instrument connectivity","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W2153973228","doi":"https://doi.org/10.1109/test.2007.4437656","mag":"2153973228"},"language":"en","primary_location":{"id":"doi:10.1109/test.2007.4437656","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2007.4437656","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071000119","display_name":"Alfred L. Crouch","orcid":"https://orcid.org/0000-0001-5846-2417"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Alfred L. Crouch","raw_affiliation_strings":["Inovys Corporation, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Inovys Corporation, Austin, TX, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5071000119"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.6128,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.91552156,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9847999811172485,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6778402328491211},{"id":"https://openalex.org/keywords/scope","display_name":"Scope (computer science)","score":0.6730282306671143},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6477351188659668},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5678455829620361},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5103244185447693},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5098637342453003},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.46861061453819275},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4529690444469452},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.4463997483253479},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.43777748942375183},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38904523849487305},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3425077795982361},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.31658610701560974},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.28753918409347534},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2572244703769684}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6778402328491211},{"id":"https://openalex.org/C2778012447","wikidata":"https://www.wikidata.org/wiki/Q1034415","display_name":"Scope (computer science)","level":2,"score":0.6730282306671143},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6477351188659668},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5678455829620361},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5103244185447693},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5098637342453003},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.46861061453819275},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4529690444469452},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.4463997483253479},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.43777748942375183},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38904523849487305},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3425077795982361},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.31658610701560974},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.28753918409347534},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2572244703769684},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2007.4437656","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2007.4437656","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"id":"https://metadata.un.org/sdg/17","display_name":"Partnerships for the goals"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2028504835","https://openalex.org/W2089476686","https://openalex.org/W2096634353","https://openalex.org/W2128285650","https://openalex.org/W6678916954"],"related_works":["https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2051956260","https://openalex.org/W2526300902","https://openalex.org/W2170504327","https://openalex.org/W1977171228","https://openalex.org/W2121963733","https://openalex.org/W1990901299","https://openalex.org/W1985308002","https://openalex.org/W2789349722"],"abstract_inverted_index":{"In":[0],"recent":[1],"times,":[2],"the":[3,38,81,114],"1149.1":[4,82],"TAP":[5,7],"and":[6,45,55,57,76,85,112,116],"controller":[8,83],"have":[9],"begun":[10],"to":[11,26,36,73,110],"play":[12],"a":[13,30,87,91,98,108],"more":[14,89],"important":[15],"role":[16],"in":[17],"accessing":[18],"embedded":[19],"logic":[20,54,60],"that":[21,102],"is":[22,103],"not":[23],"specifically":[24],"limited":[25],"1149.1's":[27],"scope":[28],"as":[29,62,107],"board-test":[31],"standard.":[32],"This":[33],"logic,":[34],"referred":[35],"by":[37],"generic":[39],"term":[40],"instruments,":[41],"includes":[42],"manufacturing":[43],"test":[44],"design-for-test":[46],"(DFT)":[47],"logic;":[48,51],"design-for-debug/diagnosis":[49],"(DFD)":[50],"design-for-yield":[52],"(DFY)":[53],"monitors;":[56],"in-system":[58],"verification":[59],"(such":[61],"hardware":[63,99],"assertions).":[64],"The":[65],"P1687":[66],"IJTAG":[67],"standard":[68],"working":[69],"group":[70],"was":[71],"created":[72],"investigate":[74,111],"formalizing":[75],"standardizing":[77],"this":[78],"use":[79],"of":[80,94],"-":[84],"after":[86],"little":[88],"than":[90],"years":[92],"worth":[93],"effort":[95],"has":[96],"produced":[97],"architecture":[100],"proposal":[101],"currently":[104],"being":[105],"used":[106],"strawman":[109],"develop":[113],"description":[115],"protocol":[117],"language":[118],"effort.":[119]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
