{"id":"https://openalex.org/W2056971036","doi":"https://doi.org/10.1109/test.2007.4437635","title":"Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis","display_name":"Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W2056971036","doi":"https://doi.org/10.1109/test.2007.4437635","mag":"2056971036"},"language":"en","primary_location":{"id":"doi:10.1109/test.2007.4437635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2007.4437635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113615776","display_name":"Soumitra Bose","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Soumitra Bose","raw_affiliation_strings":["Design Technology, Intel Corporation, Folsom, CA, USA","Design Technol., Intel Corp., Folsom, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Design Technology, Intel Corporation, Folsom, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Design Technol., Intel Corp., Folsom, CA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084081268","display_name":"Vishwani D. Agrawal","orcid":"https://orcid.org/0000-0002-7121-5979"},"institutions":[{"id":"https://openalex.org/I82497590","display_name":"Auburn University","ror":"https://ror.org/02v80fc35","country_code":"US","type":"education","lineage":["https://openalex.org/I82497590"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vishwani D. Agrawal","raw_affiliation_strings":["Department of ECE, Aubum University, Auburn, AL, USA","Department of ECE, Auburn University, Auburn, AL 36849 USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, Aubum University, Auburn, AL, USA","institution_ids":["https://openalex.org/I82497590"]},{"raw_affiliation_string":"Department of ECE, Auburn University, Auburn, AL 36849 USA","institution_ids":["https://openalex.org/I82497590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.09687291,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/tree-traversal","display_name":"Tree traversal","score":0.8179570436477661},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.7741086483001709},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7593076825141907},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6641970872879028},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.6374972462654114},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5497975945472717},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.5255405306816101},{"id":"https://openalex.org/keywords/graph-traversal","display_name":"Graph traversal","score":0.48198598623275757},{"id":"https://openalex.org/keywords/entropy","display_name":"Entropy (arrow of time)","score":0.4717997610569},{"id":"https://openalex.org/keywords/sequence","display_name":"Sequence (biology)","score":0.44274309277534485},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4396829605102539},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.387179970741272},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3721194267272949},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.25592002272605896},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12175822257995605},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.09153413772583008}],"concepts":[{"id":"https://openalex.org/C140745168","wikidata":"https://www.wikidata.org/wiki/Q1210082","display_name":"Tree traversal","level":2,"score":0.8179570436477661},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.7741086483001709},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7593076825141907},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6641970872879028},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.6374972462654114},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5497975945472717},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.5255405306816101},{"id":"https://openalex.org/C96333769","wikidata":"https://www.wikidata.org/wiki/Q907955","display_name":"Graph traversal","level":3,"score":0.48198598623275757},{"id":"https://openalex.org/C106301342","wikidata":"https://www.wikidata.org/wiki/Q4117933","display_name":"Entropy (arrow of time)","level":2,"score":0.4717997610569},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.44274309277534485},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4396829605102539},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.387179970741272},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3721194267272949},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.25592002272605896},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12175822257995605},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.09153413772583008},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/test.2007.4437635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2007.4437635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Test Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.129.5933","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.129.5933","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eng.auburn.edu/~vagrawal/TALKS/seq.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1655990431","https://openalex.org/W1964839541","https://openalex.org/W1978303825","https://openalex.org/W2002089154","https://openalex.org/W2021218329","https://openalex.org/W2022549597","https://openalex.org/W2061310904","https://openalex.org/W2069246068","https://openalex.org/W2076000316","https://openalex.org/W2085966211","https://openalex.org/W2096247094","https://openalex.org/W2103868175","https://openalex.org/W2110404100","https://openalex.org/W2121616053","https://openalex.org/W2133067315","https://openalex.org/W4302339081"],"related_works":["https://openalex.org/W2200188075","https://openalex.org/W4230405657","https://openalex.org/W4254594467","https://openalex.org/W4252596799","https://openalex.org/W244044452","https://openalex.org/W2552915643","https://openalex.org/W3213135344","https://openalex.org/W3183956626","https://openalex.org/W170547082","https://openalex.org/W2136735429"],"abstract_inverted_index":{"Stuck":[0],"fault":[1],"coverage":[2,51,116],"estimation":[3,117],"for":[4,18,46,106],"sequential":[5,88],"circuits":[6,83],"relies":[7],"on":[8],"a":[9,29,73],"time":[10],"expansion":[11],"model,":[12],"where":[13],"combinational":[14],"techniques":[15],"are":[16,23,34],"employed":[17],"each":[19],"time-frame.":[20],"Faults":[21],"that":[22,48,60,96,111],"hard":[24],"to":[25,38,54,62,101],"detect":[26],"and":[27],"require":[28],"particular":[30],"sequence":[31,66],"of":[32,67,87],"states":[33],"often":[35],"incorrectly":[36],"estimated":[37],"be":[39,102],"detected.":[40],"This":[41,69],"problem":[42],"is":[43],"more":[44],"evident":[45],"designs":[47],"exhibit":[49],"low":[50,55],"either":[52],"due":[53],"testability":[56],"or":[57],"insufficient":[58],"vectors":[59],"fail":[61],"exercise":[63],"the":[64,98,115],"required":[65],"states.":[68],"paper":[70],"illustrates":[71],"how":[72],"simple":[74],"state":[75,99],"traversal":[76],"analysis":[77],"can":[78],"mitigate":[79],"this":[80,112],"problem.":[81],"For":[82],"with":[84],"large":[85],"number":[86],"elements,":[89],"we":[90],"propose":[91],"an":[92],"entropy":[93],"based":[94],"technique":[95,113],"collapses":[97],"graph":[100],"analyzed.":[103],"Experimental":[104],"results":[105],"larger":[107],"ISCAS":[108],"benchmarks":[109],"show":[110],"reduces":[114],"error":[118],"by":[119],"as":[120,122],"much":[121],"50%.":[123]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
