{"id":"https://openalex.org/W2110881494","doi":"https://doi.org/10.1109/test.2007.4437610","title":"Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation","display_name":"Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W2110881494","doi":"https://doi.org/10.1109/test.2007.4437610","mag":"2110881494"},"language":"en","primary_location":{"id":"doi:10.1109/test.2007.4437610","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2007.4437610","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061053271","display_name":"Anis Uzzaman","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anis Uzzaman","raw_affiliation_strings":["Cadence Design Systems, Inc., Endicott, NY, USA","Cadence Design Systems Inc., Endicott, NY#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., Endicott, NY, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc., Endicott, NY#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004241278","display_name":"Bibo Li","orcid":"https://orcid.org/0000-0001-5804-9876"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bibo Li","raw_affiliation_strings":["Cadence Design Systems, Inc., Endicott, NY, USA","Cadence Design Systems Inc., Endicott, NY#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., Endicott, NY, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc., Endicott, NY#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108800422","display_name":"Tom Snethen","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tom Snethen","raw_affiliation_strings":["Cadence Design Systems, Inc., Endicott, NY, USA","Cadence Design Systems Inc., Endicott, NY#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., Endicott, NY, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc., Endicott, NY#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006214290","display_name":"Brion Keller","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brion Keller","raw_affiliation_strings":["Cadence Design Systems, Inc., Endicott, NY, USA","Cadence Design Systems Inc., Endicott, NY#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Inc., Endicott, NY, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Cadence Design Systems Inc., Endicott, NY#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078137581","display_name":"Gary Grise","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gary Grise","raw_affiliation_strings":["International Business Machines, Inc., Burlington, VT, USA","International Business Machines, Inc., Burlington, Vermont, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"International Business Machines, Inc., Burlington, VT, USA","institution_ids":["https://openalex.org/I1341412227"]},{"raw_affiliation_string":"International Business Machines, Inc., Burlington, Vermont, USA","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6369,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.72085684,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.7160871624946594},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6947413086891174},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5366529822349548},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5113281607627869},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5029968619346619},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.48468688130378723},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4807712435722351},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4795474708080292},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.4565337598323822},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.44006338715553284},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3922613561153412},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.3919767439365387},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3748452365398407},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3642504811286926},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18748876452445984},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.17988720536231995},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16940262913703918},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11697494983673096},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09720593690872192}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.7160871624946594},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6947413086891174},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5366529822349548},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5113281607627869},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5029968619346619},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.48468688130378723},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4807712435722351},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4795474708080292},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.4565337598323822},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.44006338715553284},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3922613561153412},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.3919767439365387},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3748452365398407},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3642504811286926},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18748876452445984},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.17988720536231995},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16940262913703918},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11697494983673096},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09720593690872192}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2007.4437610","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2007.4437610","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W197391467","https://openalex.org/W1484052325","https://openalex.org/W1583304273","https://openalex.org/W1915857416","https://openalex.org/W2106588126","https://openalex.org/W2127111927","https://openalex.org/W2154665706","https://openalex.org/W2168916081","https://openalex.org/W6607990715"],"related_works":["https://openalex.org/W3013792460","https://openalex.org/W1528933814","https://openalex.org/W3117015220","https://openalex.org/W1553835358","https://openalex.org/W1511802890","https://openalex.org/W2102777336","https://openalex.org/W2490069675","https://openalex.org/W1607849496","https://openalex.org/W2477544739","https://openalex.org/W3105918491"],"abstract_inverted_index":{"Although":[0],"on-product":[1],"clock":[2],"generation":[3],"(OPCG)":[4],"has":[5,20],"been":[6,22],"used":[7],"for":[8,88,96],"many":[9],"years,":[10],"often":[11],"in":[12,53],"conjunction":[13],"with":[14,44,90],"Logic":[15],"and":[16,31,72,100],"Memory":[17],"BIST,":[18],"it":[19,77],"usually":[21],"a":[23,62,86],"very":[24],"manual":[25],"process":[26],"to":[27,35,60,64],"identify":[28],"the":[29,32,45,66,69,73,91],"cut-points":[30],"OPCG":[33,46,51,70,95],"behavior":[34],"ATPG":[36,99],"tools":[37],"so":[38],"they":[39],"can":[40,78],"avoid":[41],"dealing":[42,89],"directly":[43],"logic.":[47],"To":[48],"support":[49],"programmable":[50,92],"logic":[52,71],"an":[54],"ASIC":[55],"methodology":[56],"flow":[57],"required":[58],"us":[59],"find":[61],"way":[63],"automate":[65],"handling":[67],"of":[68,94],"various":[74],"clocking":[75],"sequences":[76],"produce.":[79],"This":[80],"paper":[81],"describes":[82],"how":[83],"we":[84],"provide":[85],"means":[87],"aspects":[93],"use":[97],"during":[98],"shows":[101],"some":[102],"results.":[103]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}