{"id":"https://openalex.org/W2161961203","doi":"https://doi.org/10.1109/test.2005.1584066","title":"Testing throughput computing interconnect topologies with tbits/sec bandwidth in manufacturing and in field","display_name":"Testing throughput computing interconnect topologies with tbits/sec bandwidth in manufacturing and in field","publication_year":2006,"publication_date":"2006-02-06","ids":{"openalex":"https://openalex.org/W2161961203","doi":"https://doi.org/10.1109/test.2005.1584066","mag":"2161961203"},"language":"en","primary_location":{"id":"doi:10.1109/test.2005.1584066","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2005.1584066","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Conference on Test, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053036341","display_name":"Ishwar Parulkar","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"I. Parulkar","raw_affiliation_strings":["Scalable Systems Group, Sun Microsystems, Inc., USA"],"affiliations":[{"raw_affiliation_string":"Scalable Systems Group, Sun Microsystems, Inc., USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062027635","display_name":"Dawei Huang","orcid":"https://orcid.org/0000-0002-4496-2354"},"institutions":[{"id":"https://openalex.org/I1342911587","display_name":"Oracle (United States)","ror":"https://ror.org/006c77m33","country_code":"US","type":"company","lineage":["https://openalex.org/I1342911587"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dawei Huang","raw_affiliation_strings":["Scalable Systems Group, Sun Microsystems, Inc., USA","Scalable Syst. Group, Sun Microsystems, Inc., Santa Clara, CA"],"affiliations":[{"raw_affiliation_string":"Scalable Systems Group, Sun Microsystems, Inc., USA","institution_ids":[]},{"raw_affiliation_string":"Scalable Syst. Group, Sun Microsystems, Inc., Santa Clara, CA","institution_ids":["https://openalex.org/I1342911587"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056918721","display_name":"Lee Russell O. Chua","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"L. Chua","raw_affiliation_strings":["Scalable Systems Group, Sun Microsystems, Inc., USA"],"affiliations":[{"raw_affiliation_string":"Scalable Systems Group, Sun Microsystems, Inc., USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064848690","display_name":"Drew Doblar","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"D. Doblar","raw_affiliation_strings":["Scalable Systems Group, Sun Microsystems, Inc., USA"],"affiliations":[{"raw_affiliation_string":"Scalable Systems Group, Sun Microsystems, Inc., USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5053036341"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.5086,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.89566783,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1000","last_page":"1008"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7960675954818726},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.6890257596969604},{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.6618571281433105},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6532204151153564},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6221544742584229},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6185199022293091},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6094601154327393},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43978071212768555},{"id":"https://openalex.org/keywords/transceiver","display_name":"Transceiver","score":0.424925297498703},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3820112943649292},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32645323872566223},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3067099452018738},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2665071487426758},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.22749164700508118},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.16662174463272095},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1366913914680481}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7960675954818726},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.6890257596969604},{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.6618571281433105},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6532204151153564},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6221544742584229},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6185199022293091},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6094601154327393},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43978071212768555},{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.424925297498703},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3820112943649292},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32645323872566223},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3067099452018738},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2665071487426758},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.22749164700508118},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.16662174463272095},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1366913914680481},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2005.1584066","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2005.1584066","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Conference on Test, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.46000000834465027,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1566040143","https://openalex.org/W1575728663","https://openalex.org/W1604279453","https://openalex.org/W1998210153","https://openalex.org/W2000167488","https://openalex.org/W2094754158","https://openalex.org/W2110454476","https://openalex.org/W2113497322","https://openalex.org/W2136969326","https://openalex.org/W2156477850","https://openalex.org/W2166766585","https://openalex.org/W6649920655"],"related_works":["https://openalex.org/W2048019328","https://openalex.org/W2130047965","https://openalex.org/W3145088891","https://openalex.org/W3087888791","https://openalex.org/W2957422867","https://openalex.org/W3160420002","https://openalex.org/W2382232495","https://openalex.org/W2734818042","https://openalex.org/W2131433104","https://openalex.org/W4210385926"],"abstract_inverted_index":{"The":[0],"next":[1],"generation":[2],"of":[3,15,18,40,64],"throughput":[4],"computing":[5],"systems":[6],"designed":[7],"by":[8],"Sun":[9],"Microsystems":[10],"require":[11],"interconnect":[12,68],"with":[13],"bandwidth":[14,25],"the":[16,45,55],"order":[17],"Tbits/sec.":[19],"Interconnect":[20],"topologies":[21],"for":[22,58],"such":[23,65],"high":[24],"are":[26],"based":[27],"on":[28,34],"a":[29],"few":[30],"hundred":[31],"SerDes":[32],"I/Os":[33,42,66],"chips":[35],"operating":[36],"at":[37,43],"multi-Gbps.":[38],"Testing":[39],"these":[41],"only":[44],"component":[46],"level":[47],"is":[48],"inadequate.":[49],"In":[50],"this":[51],"paper,":[52],"we":[53],"describe":[54],"design-for-testability":[56],"features":[57],"system":[59],"manufacturing":[60],"and":[61,67],"on-line":[62],"test":[63]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
