{"id":"https://openalex.org/W2154711067","doi":"https://doi.org/10.1109/test.2005.1583987","title":"Automated mapping of pre-computed module-level test sequences to processor instructions","display_name":"Automated mapping of pre-computed module-level test sequences to processor instructions","publication_year":2006,"publication_date":"2006-02-06","ids":{"openalex":"https://openalex.org/W2154711067","doi":"https://doi.org/10.1109/test.2005.1583987","mag":"2154711067"},"language":"en","primary_location":{"id":"doi:10.1109/test.2005.1583987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2005.1583987","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Conference on Test, 2005.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005706700","display_name":"Sankar Gurumurthy","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Gurumurthy","raw_affiliation_strings":["University of Texas at Austin, Austin, TX, US"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Texas at Austin, Austin, TX, US","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034719762","display_name":"Shobha Vasudevan","orcid":"https://orcid.org/0000-0002-6995-3219"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Vasudevan","raw_affiliation_strings":["Computer Engineering Research Center, University of Texas at Austin, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Texas at Austin, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068070739","display_name":"Jacob A. Abraham","orcid":"https://orcid.org/0000-0002-5336-5631"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.A. Abraham","raw_affiliation_strings":["Computer Engineering Research Center, University of Texas at Austin, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Texas at Austin, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":44,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"294","last_page":"303"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.772863507270813},{"id":"https://openalex.org/keywords/sequence","display_name":"Sequence (biology)","score":0.5792281627655029},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5227944254875183},{"id":"https://openalex.org/keywords/property","display_name":"Property (philosophy)","score":0.5042315721511841},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4732949137687683},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4609556496143341},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.43156594038009644},{"id":"https://openalex.org/keywords/trace","display_name":"TRACE (psycholinguistics)","score":0.42722076177597046},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41794854402542114},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.375137597322464}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.772863507270813},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.5792281627655029},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5227944254875183},{"id":"https://openalex.org/C189950617","wikidata":"https://www.wikidata.org/wiki/Q937228","display_name":"Property (philosophy)","level":2,"score":0.5042315721511841},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4732949137687683},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4609556496143341},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.43156594038009644},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.42722076177597046},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41794854402542114},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.375137597322464},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/test.2005.1583987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2005.1583987","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Conference on Test, 2005.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.125.6471","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.125.6471","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://sankarng.googlepages.com/itc05.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1506588809","https://openalex.org/W1511398680","https://openalex.org/W1522416322","https://openalex.org/W1787074469","https://openalex.org/W1876406499","https://openalex.org/W1891950198","https://openalex.org/W1905213452","https://openalex.org/W2004437077","https://openalex.org/W2103534830","https://openalex.org/W2111785162","https://openalex.org/W2115649468","https://openalex.org/W2124628240","https://openalex.org/W2126042558","https://openalex.org/W2127936537","https://openalex.org/W2132845196","https://openalex.org/W2135931142","https://openalex.org/W2141476458","https://openalex.org/W2156747864","https://openalex.org/W2171599508","https://openalex.org/W4230587734","https://openalex.org/W4232404949","https://openalex.org/W4233176001","https://openalex.org/W4247903400","https://openalex.org/W6630589821","https://openalex.org/W6631317423","https://openalex.org/W6651354974","https://openalex.org/W6676649663"],"related_works":["https://openalex.org/W2091833418","https://openalex.org/W2913077774","https://openalex.org/W4256030018","https://openalex.org/W2145089576","https://openalex.org/W2021253405","https://openalex.org/W1986228509","https://openalex.org/W2147400189","https://openalex.org/W1600468096","https://openalex.org/W2340957901","https://openalex.org/W1991935474"],"abstract_inverted_index":{"Executing":[0],"instructions":[1],"from":[2],"the":[3,10,18,52,76,79,95,103,111,116,121,130,158],"cache":[4],"has":[5,28,126],"been":[6,29],"shown":[7],"to":[8,32,46,58,83,114,140,149,161],"improve":[9],"defect":[11],"coverage":[12],"of":[13,55,60,78,132,147],"real":[14],"chips.":[15],"However,":[16],"although":[17],"faults":[19],"detected":[20],"by":[21],"such":[22],"tests":[23],"can":[24,107,137,153],"be":[25,108,138,155],"determined,":[26],"there":[27],"no":[30,127],"technique":[31,45,125],"target":[33],"test":[34,49,66,118,133,142],"generation":[35],"for":[36,94,144],"an":[37],"undetected":[38],"fault.":[39],"This":[40,99,124],"paper":[41],"presents":[42],"a":[43,56,71,84,92],"novel":[44],"map":[47,141],"pre-computed":[48,65,117],"sequences":[50,59,143],"at":[51,110,120],"module":[53,63,122],"level":[54,64],"processor,":[57],"instructions.":[61,151],"The":[62,88],"sequence":[67,105,119],"is":[68,81],"translated":[69],"into":[70],"temporal":[72,96],"logic":[73,97],"property":[74,80],"and":[75],"negation":[77],"passed":[82],"bounded":[85],"model":[86,89],"checker.":[87],"checker":[90],"produces":[91],"counter-example":[93,100],"property.":[98],"trace":[101],"contains":[102],"instruction":[104],"that":[106],"applied":[109],"primary":[112],"inputs":[113],"produce":[115,162],"inputs.":[123],"restrictions":[128],"on":[129],"type":[131],"sequences,":[134],"so":[135],"it":[136],"used":[139,156],"any":[145],"kind":[146],"fault":[148],"processor":[150],"It":[152],"also":[154],"in":[157],"design":[159],"phase":[160],"validation":[163],"tests.":[164]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
