{"id":"https://openalex.org/W4239159012","doi":"https://doi.org/10.1109/test.2004.1387457","title":"Elimination of traditional functional testing of interface timings at Intel","display_name":"Elimination of traditional functional testing of interface timings at Intel","publication_year":2005,"publication_date":"2005-03-21","ids":{"openalex":"https://openalex.org/W4239159012","doi":"https://doi.org/10.1109/test.2004.1387457"},"language":"en","primary_location":{"id":"doi:10.1109/test.2004.1387457","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1387457","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034312378","display_name":"M. Tripp","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M. Tripp","raw_affiliation_strings":["Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071493789","display_name":"T.M. Mak","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T.M. Mak","raw_affiliation_strings":["Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010643782","display_name":"A. Meixner","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Meixner","raw_affiliation_strings":["Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5034312378"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.7734,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.76445578,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1448","last_page":"1454"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pentium","display_name":"Pentium","score":0.9453527927398682},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.727125883102417},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.592155396938324},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5900951623916626},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5544549226760864},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5115678906440735},{"id":"https://openalex.org/keywords/automatic-test-equipment","display_name":"Automatic test equipment","score":0.5077656507492065},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.47537246346473694},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45741814374923706},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.207227885723114},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17503473162651062},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.14908632636070251}],"concepts":[{"id":"https://openalex.org/C46268123","wikidata":"https://www.wikidata.org/wiki/Q214314","display_name":"Pentium","level":2,"score":0.9453527927398682},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.727125883102417},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.592155396938324},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5900951623916626},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5544549226760864},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5115678906440735},{"id":"https://openalex.org/C141842801","wikidata":"https://www.wikidata.org/wiki/Q363815","display_name":"Automatic test equipment","level":3,"score":0.5077656507492065},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.47537246346473694},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45741814374923706},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.207227885723114},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17503473162651062},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.14908632636070251},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2004.1387457","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1387457","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1657391569","https://openalex.org/W1709517310","https://openalex.org/W1930127001","https://openalex.org/W2149364102","https://openalex.org/W2158444496","https://openalex.org/W2161839702"],"related_works":["https://openalex.org/W1597195064","https://openalex.org/W1545378222","https://openalex.org/W2915007006","https://openalex.org/W3164835776","https://openalex.org/W2230641373","https://openalex.org/W1560501822","https://openalex.org/W2129938370","https://openalex.org/W2039249740","https://openalex.org/W2109086232","https://openalex.org/W4240478293"],"abstract_inverted_index":{"This":[0,24],"work":[1],"summarizes":[2],"the":[3,29,39,55,85],"design":[4],"for":[5,32],"test":[6,10,34,47],"(DFT)":[7],"circuitry":[8],"and":[9,38,66],"methods":[11],"that":[12],"enabled":[13],"Intel":[14],"to":[15,41,69,83],"shift":[16,25],"away":[17],"from":[18,54],"traditional":[19],"functional":[20],"testing":[21],"of":[22,28,77],"I/O's.":[23],"was":[26],"one":[27],"key":[30,71],"enablers":[31],"automatic":[33],"equipment":[35],"(ATE)":[36],"re-use":[37],"move":[40],"lower":[42],"capability":[43],"(&":[44],"cost)":[45],"structural":[46],"platforms.":[48],"Specific":[49],"examples":[50],"include":[51],"circuit":[52],"implementations":[53],"Pentium/sup":[56],"/spl":[57],"reg//":[58],"4":[59],"processor,":[60],"high":[61,88],"volume":[62],"manufacturing":[63],"(HVM)":[64],"data,":[65],"evolutionary":[67],"changes":[68],"address":[70],"learnings.":[72],"We":[73],"close":[74],"with":[75],"indications":[76],"how":[78],"this":[79],"can":[80],"be":[81],"extended":[82],"cover":[84],"next":[86],"generation":[87],"speed":[89],"serial":[90],"like":[91],"interfaces.":[92]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}