{"id":"https://openalex.org/W1488636588","doi":"https://doi.org/10.1109/test.2004.1387443","title":"Options for high-volume test of multi-Gb/s ports","display_name":"Options for high-volume test of multi-Gb/s ports","publication_year":2005,"publication_date":"2005-03-21","ids":{"openalex":"https://openalex.org/W1488636588","doi":"https://doi.org/10.1109/test.2004.1387443","mag":"1488636588"},"language":"en","primary_location":{"id":"doi:10.1109/test.2004.1387443","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1387443","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021808887","display_name":"Julian Johnson","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"J.C. Johnson","raw_affiliation_strings":["Test Platform Architecture and Development, Intel Corporation, USA","Test Platform Archit. & Dev., Intel Corp., USA"],"affiliations":[{"raw_affiliation_string":"Test Platform Architecture and Development, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Test Platform Archit. & Dev., Intel Corp., USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5021808887"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.2578,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.54411139,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1435","last_page":"1435"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9840999841690063,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.6638411283493042},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.6283247470855713},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5962044596672058},{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.507764458656311},{"id":"https://openalex.org/keywords/serial-port","display_name":"Serial port","score":0.4886782467365265},{"id":"https://openalex.org/keywords/volume","display_name":"Volume (thermodynamics)","score":0.44152674078941345},{"id":"https://openalex.org/keywords/parallel-port","display_name":"Parallel port","score":0.42624276876449585},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36078789830207825},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34292322397232056},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.3144903779029846},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3086640238761902},{"id":"https://openalex.org/keywords/serial-communication","display_name":"Serial communication","score":0.27201002836227417},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.25644829869270325},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12393605709075928},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.07656744122505188}],"concepts":[{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.6638411283493042},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.6283247470855713},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5962044596672058},{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.507764458656311},{"id":"https://openalex.org/C102349902","wikidata":"https://www.wikidata.org/wiki/Q385390","display_name":"Serial port","level":3,"score":0.4886782467365265},{"id":"https://openalex.org/C20556612","wikidata":"https://www.wikidata.org/wiki/Q4469374","display_name":"Volume (thermodynamics)","level":2,"score":0.44152674078941345},{"id":"https://openalex.org/C202683721","wikidata":"https://www.wikidata.org/wiki/Q190440","display_name":"Parallel port","level":3,"score":0.42624276876449585},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36078789830207825},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34292322397232056},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.3144903779029846},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3086640238761902},{"id":"https://openalex.org/C51707140","wikidata":"https://www.wikidata.org/wiki/Q518280","display_name":"Serial communication","level":2,"score":0.27201002836227417},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25644829869270325},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12393605709075928},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.07656744122505188},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2004.1387443","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1387443","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2388008732","https://openalex.org/W1983539184","https://openalex.org/W2492881899","https://openalex.org/W2377431806","https://openalex.org/W2389313424","https://openalex.org/W1484277989","https://openalex.org/W1601242605","https://openalex.org/W2362383487","https://openalex.org/W2364465724","https://openalex.org/W1526795510"],"abstract_inverted_index":{"Devices":[0],"with":[1,24,60,81,101],"multi-GB/s":[2,32,115],"ports":[3],"from":[4],"a":[5,94,114],"variety":[6],"of":[7,29,43,75],"suppliers":[8],"are":[9,21,111],"shipping":[10],"in":[11,31,70],"high-volume":[12],"today.":[13],"Common":[14],"port":[15,33,46,103,116],"standards":[16],"such":[17],"as":[18,50],"PCI":[19],"Express":[20],"proliferating":[22],"along":[23],"specialty":[25],"ports.":[26],"The":[27,41,78,119],"number":[28],"lanes":[30,65],"can":[34],"usually":[35],"be":[36],"scaled":[37],"to":[38,84],"increase":[39],"bandwidth.":[40],"use":[42],"this":[44],"serial/parallel":[45],"technology":[47],"is":[48,92],"growing":[49],"its":[51],"bandwidth":[52],"scaling,":[53],"PCB":[54],"trace":[55],"out.":[56],"Traditional":[57],"SERDES":[58],"devices":[59],"only":[61],"1":[62],"or":[63],"2":[64],"had":[66],"most":[67],"yield":[68],"fallout":[69],"the":[71,76],"high-speed":[72],"serial":[73],"portion":[74],"design.":[77],"industry":[79],"responded":[80],"ATE":[82],"instruments":[83],"expose":[85],"those":[86],"defects.":[87],"Physical":[88],"layer":[89],"compliance":[90],"testing":[91],"always":[93],"challenge":[95],"and":[96],"becomes":[97],"overwhelming":[98],"when":[99],"coupled":[100],"multiple":[102],"types.":[104],"In":[105],"many":[106],"cases,":[107],"logic":[108,126],"test":[109],"patterns":[110],"applied":[112],"through":[113],"at":[117],"speed.":[118],"very":[120],"high":[121],"speed":[122],"interfaces":[123],"shows":[124],"non-deterministic":[125],"behavior.":[127]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
