{"id":"https://openalex.org/W1852582067","doi":"https://doi.org/10.1109/test.2004.1387385","title":"A DFT technique for delay fault testability and diagnostics in 32-bit high performance CMOS ALUs","display_name":"A DFT technique for delay fault testability and diagnostics in 32-bit high performance CMOS ALUs","publication_year":2005,"publication_date":"2005-03-21","ids":{"openalex":"https://openalex.org/W1852582067","doi":"https://doi.org/10.1109/test.2004.1387385","mag":"1852582067"},"language":"en","primary_location":{"id":"doi:10.1109/test.2004.1387385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1387385","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5017386059","display_name":"B. Chatterjee","orcid":"https://orcid.org/0000-0003-3698-872X"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"B. Chatterjee","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada","Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086259491","display_name":"Manoj Sachdev","orcid":"https://orcid.org/0000-0002-8256-9828"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"M. Sachdev","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada","Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103040522","display_name":"A. Keshavarzi","orcid":"https://orcid.org/0000-0001-6938-1161"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Keshavarzi","raw_affiliation_strings":["Circuits Research, Intel Labs, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Circuits Research, Intel Labs, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5017386059"],"corresponding_institution_ids":["https://openalex.org/I151746483"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.08477589,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1108","last_page":"1117"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7996547222137451},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.7282959818840027},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6408805847167969},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6272990703582764},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5198081731796265},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.5070455074310303},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.43416115641593933},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.41392824053764343},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40563657879829407},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.2650802731513977},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18348944187164307},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10164487361907959}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7996547222137451},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.7282959818840027},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6408805847167969},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6272990703582764},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5198081731796265},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.5070455074310303},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.43416115641593933},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.41392824053764343},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40563657879829407},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2650802731513977},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18348944187164307},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10164487361907959},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/test.2004.1387385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1387385","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.117.5501","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.117.5501","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.itcprogramdev.org/itc2004proc/papers/pdfs/0039_1.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.542.1378","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.542.1378","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"https://ece.uwaterloo.ca/~cdr/pubs/Bhaskar_ITC04.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1491093261","https://openalex.org/W1505584864","https://openalex.org/W1620963342","https://openalex.org/W1768857380","https://openalex.org/W1913711070","https://openalex.org/W1958909498","https://openalex.org/W2052390581","https://openalex.org/W2096735058","https://openalex.org/W2100827158","https://openalex.org/W2129563753","https://openalex.org/W2133247319","https://openalex.org/W2154188455","https://openalex.org/W2154941994","https://openalex.org/W3172772885","https://openalex.org/W4212961314","https://openalex.org/W6797258325"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W2142405811","https://openalex.org/W2114980936","https://openalex.org/W2164493372","https://openalex.org/W1594445436","https://openalex.org/W2128920253","https://openalex.org/W2164349885","https://openalex.org/W1768820276"],"abstract_inverted_index":{"Aggressive":[0],"technology":[1],"scaling":[2,85],"has":[3,18],"been":[4],"the":[5,13,21,81,93],"mainstay":[6],"of":[7,23,29,46],"digital":[8],"CMOS":[9,97],"circuit":[10],"design":[11,22],"for":[12,92,119],"past":[14],"30":[15],"years.":[16],"This":[17],"resulted":[19],"in":[20,51,71],"multi-gigahertz":[24],"microprocessors":[25],"with":[26,88,113],"unprecedented":[27],"levels":[28],"integration.":[30],"However,":[31],"this":[32,104],"is":[33],"posing":[34],"serious":[35],"challenges":[36],"to":[37,58,67,109],"IC":[38],"testing":[39],"and":[40,48,84],"long-term":[41],"reliability.":[42],"A":[43],"major":[44],"source":[45],"failures":[47],"test":[49,126],"escapes":[50],"high":[52,76],"performance":[53,77],"ICs":[54],"can":[55,106],"be":[56,107],"attributed":[57],"timing-only":[59],"parametric":[60],"failures.":[61],"We":[62,79],"implement":[63],"a":[64,72],"DFT":[65,90],"technique":[66,91,105],"detect":[68,110],"delay":[69,111],"faults":[70,112],"full":[73],"custom":[74],"32-bit":[75],"ALU.":[78],"present":[80],"energy-delay":[82],"tradeoffs":[83],"trends":[86],"associated":[87],"our":[89],"180":[94,120],"nm-65":[95],"nm":[96,121],"technologies.":[98],"In":[99],"addition,":[100],"we":[101],"demonstrate":[102],"how":[103],"used":[108],"improved":[114],"resolution":[115],"(/spl":[116],"sim/60":[117],"ps":[118],"technology)":[122],"at":[123],"relatively":[124],"low,":[125],"mode":[127],"clock":[128],"frequencies.":[129]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}