{"id":"https://openalex.org/W1483044232","doi":"https://doi.org/10.1109/test.2004.1387368","title":"Timing-independent testing of crosstalk in the presence of delay producing defects using surrogate fault models","display_name":"Timing-independent testing of crosstalk in the presence of delay producing defects using surrogate fault models","publication_year":2005,"publication_date":"2005-03-21","ids":{"openalex":"https://openalex.org/W1483044232","doi":"https://doi.org/10.1109/test.2004.1387368","mag":"1483044232"},"language":"en","primary_location":{"id":"doi:10.1109/test.2004.1387368","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1387368","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031752971","display_name":"S. Irajpour","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S. Irajpour","raw_affiliation_strings":["Department of EE-Systems, University of Southern California, Los Angeles, CA, USA","Dept. of EE-Systems, Univ. of Southern California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of EE-Systems, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"Dept. of EE-Systems, Univ. of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100601790","display_name":"Sandeep K. Gupta","orcid":"https://orcid.org/0000-0002-2585-9378"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.K. Gupta","raw_affiliation_strings":["Department of EE-Systems, University of Southern California, Los Angeles, CA, USA","Dept. of EE-Systems, Univ. of Southern California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of EE-Systems, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"Dept. of EE-Systems, Univ. of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111192060","display_name":"M.A. Breuer","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.A. Breuer","raw_affiliation_strings":["Department of EE-Systems, University of Southern California, Los Angeles, CA, USA","Dept. of EE-Systems, Univ. of Southern California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of EE-Systems, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"Dept. of EE-Systems, Univ. of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5031752971"],"corresponding_institution_ids":["https://openalex.org/I1174212"],"apc_list":null,"apc_paid":null,"fwci":2.111,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.86930999,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1024","last_page":"1033"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crosstalk","display_name":"Crosstalk","score":0.7374789714813232},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5781328082084656},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4871353805065155},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4390971064567566},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4310567080974579},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.416833758354187},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4087599813938141},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.3559233546257019},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.35510677099227905},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.18155324459075928},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18088281154632568}],"concepts":[{"id":"https://openalex.org/C169822122","wikidata":"https://www.wikidata.org/wiki/Q230187","display_name":"Crosstalk","level":2,"score":0.7374789714813232},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5781328082084656},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4871353805065155},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4390971064567566},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4310567080974579},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.416833758354187},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4087599813938141},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.3559233546257019},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.35510677099227905},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18155324459075928},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18088281154632568}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/test.2004.1387368","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1387368","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.124.8263","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.124.8263","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.itcprogramdev.org/itc2004proc/papers/pdfs/0036_1.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16","score":0.7400000095367432}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W13277579","https://openalex.org/W1556480701","https://openalex.org/W1596721108","https://openalex.org/W2005319125","https://openalex.org/W2041179462","https://openalex.org/W2079866295","https://openalex.org/W2097811636","https://openalex.org/W2098706146","https://openalex.org/W2102181378","https://openalex.org/W2112239008","https://openalex.org/W2115296652","https://openalex.org/W2116673262","https://openalex.org/W2117994896","https://openalex.org/W2119151480","https://openalex.org/W2121424172","https://openalex.org/W2123057190","https://openalex.org/W2125368263","https://openalex.org/W2135802341","https://openalex.org/W2138549077","https://openalex.org/W2158586221","https://openalex.org/W2170668491","https://openalex.org/W2171908682","https://openalex.org/W4231541540","https://openalex.org/W6600530048","https://openalex.org/W6651787432","https://openalex.org/W6674918397","https://openalex.org/W6677641026"],"related_works":["https://openalex.org/W2100329931","https://openalex.org/W3015599398","https://openalex.org/W2034656493","https://openalex.org/W4229446324","https://openalex.org/W2158805860","https://openalex.org/W2110367374","https://openalex.org/W3151506308","https://openalex.org/W1986294008","https://openalex.org/W2345182073","https://openalex.org/W1947426333"],"abstract_inverted_index":{"All":[0],"previous":[1],"approaches":[2],"for":[3,6,70,83,92,101,125,159],"generating":[4,23,89],"tests":[5,69,161],"crosstalk":[7,34,71,85,127,155],"slow-downs":[8],"are":[9,106],"timing-dependent,":[10],"i.e.,":[11],"they":[12],"use":[13],"the":[14,40,55,59,63,109,134,138,154],"nominal":[15],"values":[16,57],"of":[17,26,42,81,118,140,183],"gate":[18],"and":[19,45,52,88,144,157],"wire":[20],"delays":[21],"while":[22],"tests.":[24],"None":[25],"these":[27],"methodologies":[28],"can":[29],"be":[30,37,163],"used":[31],"when":[32],"a":[33,79,90,99,116,126,150,168],"slow-down":[35,86,128],"must":[36,104,162],"considered":[38],"in":[39,137],"presence":[41,139],"process":[43],"variations":[44,51,143],"delay":[46,56,111,142,145],"producing":[47,146],"defects,":[48],"since":[49],"such":[50],"defects":[53],"change":[54],"from":[58],"nominal.":[60],"We":[61,148,175],"present":[62,149,176],"first":[64],"timing-independent":[65,96],"approach":[66],"to":[67,132,152],"generate":[68],"slow-downs.":[72],"The":[73,95],"framework":[74],"is":[75,130],"based":[76],"upon":[77],"defining":[78],"set":[80,117],"surrogates":[82,158],"each":[84,93,102],"target":[87,129],"test":[91,100,169],"surrogate.":[94],"conditions":[97],"that":[98,115,121,171],"surrogate":[103,124],"satisfy":[105],"presented.":[107],"Under":[108],"pin-to-pin":[110],"model,":[112],"we":[113,172],"prove":[114],"two-vector":[119],"sequences":[120],"covers":[122],"every":[123],"guaranteed":[131],"detect":[133],"target,":[135],"even":[136],"arbitrary":[141],"defects.":[147],"method":[151],"identify":[153],"targets":[156],"which":[160],"generated":[164],"as":[165,167],"well":[166],"generator":[170],"have":[173],"implemented.":[174],"extensive":[177],"experimental":[178],"results":[179],"using":[180],"combinational":[181],"parts":[182],"ISCAS":[184],"89":[185],"circuits.":[186]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}