{"id":"https://openalex.org/W2163537934","doi":"https://doi.org/10.1109/test.2004.1387001","title":"Interconnect delay testings of designs on programmable logic devices","display_name":"Interconnect delay testings of designs on programmable logic devices","publication_year":2005,"publication_date":"2005-03-07","ids":{"openalex":"https://openalex.org/W2163537934","doi":"https://doi.org/10.1109/test.2004.1387001","mag":"2163537934"},"language":"en","primary_location":{"id":"doi:10.1109/test.2004.1387001","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1387001","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064445713","display_name":"Mehdi B. Tahoori","orcid":"https://orcid.org/0000-0002-8829-5610"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M.B. Tahoori","raw_affiliation_strings":["Department of ECE, Northeastern University, Boston, MA, USA"],"affiliations":[{"raw_affiliation_string":"Department of ECE, Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036312663","display_name":"Subhasish Mitra","orcid":"https://orcid.org/0000-0002-5572-5194"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Mitra","raw_affiliation_strings":["Intel Corporation, Sacramento, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Sacramento, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5064445713"],"corresponding_institution_ids":["https://openalex.org/I12912129"],"apc_list":null,"apc_paid":null,"fwci":1.0312,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.79347364,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"635","last_page":"644"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.687046468257904},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6539276242256165},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.6075085401535034},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5999899506568909},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5789450407028198},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5711652040481567},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5265322327613831},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.5237745642662048},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5209276080131531},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.47994664311408997},{"id":"https://openalex.org/keywords/erasable-programmable-logic-device","display_name":"Erasable programmable logic device","score":0.46399304270744324},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.46321019530296326},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.42031192779541016},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.41983750462532043},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.41822534799575806},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37140512466430664},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3226394057273865},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22176715731620789},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.202998548746109},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.1845548450946808},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14284729957580566},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.12221622467041016},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07787492871284485}],"concepts":[{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.687046468257904},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6539276242256165},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.6075085401535034},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5999899506568909},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5789450407028198},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5711652040481567},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5265322327613831},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.5237745642662048},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5209276080131531},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.47994664311408997},{"id":"https://openalex.org/C110050671","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Erasable programmable logic device","level":5,"score":0.46399304270744324},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.46321019530296326},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.42031192779541016},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.41983750462532043},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.41822534799575806},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37140512466430664},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3226394057273865},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22176715731620789},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.202998548746109},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.1845548450946808},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14284729957580566},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.12221622467041016},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07787492871284485},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2004.1387001","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1387001","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1526642634","https://openalex.org/W1532888190","https://openalex.org/W1644626461","https://openalex.org/W1914809015","https://openalex.org/W1916533169","https://openalex.org/W1961788500","https://openalex.org/W2032134808","https://openalex.org/W2084641700","https://openalex.org/W2102105233","https://openalex.org/W2102927569","https://openalex.org/W2107375256","https://openalex.org/W2108529592","https://openalex.org/W2112239008","https://openalex.org/W2119588320","https://openalex.org/W2127382553","https://openalex.org/W2136841933","https://openalex.org/W2137337804","https://openalex.org/W2142982703","https://openalex.org/W2143974498","https://openalex.org/W2150107614","https://openalex.org/W2151271718","https://openalex.org/W2153887537","https://openalex.org/W2157074294","https://openalex.org/W2162529266","https://openalex.org/W2163865290","https://openalex.org/W2171908682","https://openalex.org/W2752573522","https://openalex.org/W2752885492","https://openalex.org/W3145128584","https://openalex.org/W6684360715","https://openalex.org/W7029321148"],"related_works":["https://openalex.org/W1528933814","https://openalex.org/W3013792460","https://openalex.org/W3117015220","https://openalex.org/W2014165129","https://openalex.org/W1904803855","https://openalex.org/W3022525969","https://openalex.org/W2376859467","https://openalex.org/W2466591189","https://openalex.org/W4389045693","https://openalex.org/W2054740893"],"abstract_inverted_index":{"Very":[0],"thorough":[1],"interconnect":[2],"delay":[3,28],"testing":[4],"technique":[5,22],"for":[6],"designs":[7],"implemented":[8],"on":[9,30,64],"programmable":[10],"logic":[11],"devices,":[12],"such":[13],"as":[14],"FPGAs,":[15],"is":[16,59,80],"presented":[17,21],"(application-dependent":[18],"test).":[19],"The":[20,53],"achieves":[23],"1)":[24],"100%":[25,38,44],"robust":[26],"path":[27],"coverage":[29],"all":[31,49],"the":[32,35,65,68,75],"paths":[33],"in":[34],"design,":[36],"2)":[37],"transition":[39,47],"fault":[40],"coverage,":[41,46],"and":[42,78],"3)":[43],"TARO":[45],"to":[48,73],"reachable":[50],"primary":[51],"outputs.":[52],"required":[54],"number":[55],"of":[56,67],"test":[57,76],"configurations":[58,79],"two":[60],"or":[61],"four":[62],"depending":[63],"structure":[66],"design.":[69],"An":[70],"algorithmic":[71],"approach":[72],"generate":[74],"vectors":[77],"presented.":[81]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}