{"id":"https://openalex.org/W1589327193","doi":"https://doi.org/10.1109/test.2004.1386968","title":"Testing micropipelined asynchronous circuits","display_name":"Testing micropipelined asynchronous circuits","publication_year":2005,"publication_date":"2005-03-21","ids":{"openalex":"https://openalex.org/W1589327193","doi":"https://doi.org/10.1109/test.2004.1386968","mag":"1589327193"},"language":"en","primary_location":{"id":"doi:10.1109/test.2004.1386968","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1386968","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031361870","display_name":"M.L. King","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]},{"id":"https://openalex.org/I1304256225","display_name":"University of Wisconsin System","ror":"https://ror.org/03ydkyb10","country_code":"US","type":"education","lineage":["https://openalex.org/I1304256225"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M.L. King","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA","Dept. of Electr. & Comput Eng., Wisconsin Univ., Madison, WI, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA","institution_ids":["https://openalex.org/I135310074"]},{"raw_affiliation_string":"Dept. of Electr. & Comput Eng., Wisconsin Univ., Madison, WI, USA","institution_ids":["https://openalex.org/I1304256225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110218098","display_name":"Kewal K. Saluja","orcid":null},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]},{"id":"https://openalex.org/I1304256225","display_name":"University of Wisconsin System","ror":"https://ror.org/03ydkyb10","country_code":"US","type":"education","lineage":["https://openalex.org/I1304256225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K.K. Saluja","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA","Dept. of Electr. & Comput Eng., Wisconsin Univ., Madison, WI, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA","institution_ids":["https://openalex.org/I135310074"]},{"raw_affiliation_string":"Dept. of Electr. & Comput Eng., Wisconsin Univ., Madison, WI, USA","institution_ids":["https://openalex.org/I1304256225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5031361870"],"corresponding_institution_ids":["https://openalex.org/I1304256225","https://openalex.org/I135310074"],"apc_list":null,"apc_paid":null,"fwci":1.0552,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.77666804,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"329","last_page":"338"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.9007155299186707},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8610203266143799},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.788047194480896},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6942532658576965},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6645683646202087},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5061933398246765},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4572434723377228},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.44415083527565},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3567037582397461},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34701007604599},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3252500891685486},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1928788125514984},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.15505436062812805},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10703772306442261},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.06976506114006042},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.06782019138336182},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.061164677143096924}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.9007155299186707},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8610203266143799},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.788047194480896},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6942532658576965},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6645683646202087},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5061933398246765},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4572434723377228},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.44415083527565},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3567037582397461},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34701007604599},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3252500891685486},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1928788125514984},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15505436062812805},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10703772306442261},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.06976506114006042},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.06782019138336182},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.061164677143096924}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/test.2004.1386968","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1386968","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.132.9320","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.132.9320","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.itcprogramdev.org/itc2004proc/papers/pdfs/0012_1.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2013129990","https://openalex.org/W2031699118","https://openalex.org/W2087895643","https://openalex.org/W2103413444","https://openalex.org/W2107163997","https://openalex.org/W2110259743","https://openalex.org/W2147573597","https://openalex.org/W2147909695","https://openalex.org/W2156476900","https://openalex.org/W2160160584","https://openalex.org/W2160162958","https://openalex.org/W2168634757","https://openalex.org/W2296552982","https://openalex.org/W4231905827","https://openalex.org/W4245804582"],"related_works":["https://openalex.org/W1948903516","https://openalex.org/W2107525390","https://openalex.org/W1993985975","https://openalex.org/W2146990170","https://openalex.org/W2187164010","https://openalex.org/W4312516786","https://openalex.org/W2085028021","https://openalex.org/W2138474603","https://openalex.org/W1589327193","https://openalex.org/W2373135325"],"abstract_inverted_index":{"Despite":[0],"advances":[1],"in":[2,13,71],"the":[3,31,36,72,86,92],"design":[4,17,93],"of":[5,88],"asynchronous":[6,32,47],"circuits,":[7],"little":[8],"progress":[9],"has":[10],"been":[11],"made":[12],"their":[14,61],"testing":[15,27,43,103],"or":[16],"for":[18,26,42,54,75,78],"testability.":[19],"This":[20],"work":[21],"proposes":[22],"a":[23,79],"new":[24],"strategy":[25],"micropipelines,":[28],"by":[29],"treating":[30,46],"elements,":[33],"such":[34],"as":[35,38,49],"C-element,":[37],"atomic":[39],"state":[40,51],"elements":[41,48],"purposes.":[44],"By":[45],"finite":[50],"machines,":[52],"tests":[53],"these":[55],"can":[56],"be":[57],"generated":[58],"that":[59,84],"verify":[60],"correct":[62],"operation":[63],"and":[64],"also":[65,82],"detect":[66],"nearly":[67],"all":[68],"testable":[69],"faults":[70],"circuit.":[73],"Design":[74],"testability":[76,98],"methods":[77],"micropipeline":[80,102],"are":[81],"presented":[83],"reduce":[85],"amount":[87],"hardware":[89],"added":[90],"to":[91,100],"while":[94],"increasing":[95],"its":[96],"overall":[97],"compared":[99],"other":[101],"methods.":[104]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
