{"id":"https://openalex.org/W1959076962","doi":"https://doi.org/10.1109/test.2004.1386935","title":"An optimized DFT and test pattern generation strategy for an Intel high performance microprocessor","display_name":"An optimized DFT and test pattern generation strategy for an Intel high performance microprocessor","publication_year":2005,"publication_date":"2005-03-21","ids":{"openalex":"https://openalex.org/W1959076962","doi":"https://doi.org/10.1109/test.2004.1386935","mag":"1959076962"},"language":"en","primary_location":{"id":"doi:10.1109/test.2004.1386935","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1386935","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101720948","display_name":"D.M. Wu","orcid":"https://orcid.org/0000-0002-3591-7754"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":true,"raw_author_name":"D.M. Wu","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111906591","display_name":"Min-Hsien Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"M. Lin","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113985660","display_name":"M. Swetha Reddy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"M. Reddy","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071113429","display_name":"Tarif M Jaber","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"T. Jaber","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016591358","display_name":"A. Sabbavarapu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"A. Sabbavarapu","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038294802","display_name":"L.E. Thatcher","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"L. Thatcher","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5101720948"],"corresponding_institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"],"apc_list":null,"apc_paid":null,"fwci":2.8359,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.90433673,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"38","last_page":"47"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.8662577867507935},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.67174232006073},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.6164836287498474},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6067795157432556},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5766246318817139},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5152013897895813},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4761107861995697},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3766217827796936},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2306634485721588},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18536511063575745},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.12098795175552368},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.11932408809661865},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.11434414982795715},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.09480464458465576}],"concepts":[{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.8662577867507935},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.67174232006073},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6164836287498474},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6067795157432556},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5766246318817139},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5152013897895813},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4761107861995697},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3766217827796936},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2306634485721588},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18536511063575745},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.12098795175552368},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.11932408809661865},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.11434414982795715},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.09480464458465576}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2004.1386935","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2004.1386935","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 International Conferce on Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W30844492","https://openalex.org/W1484052325","https://openalex.org/W1763985980","https://openalex.org/W1819226324","https://openalex.org/W1891950198","https://openalex.org/W1903669731","https://openalex.org/W2102127226","https://openalex.org/W2117771660","https://openalex.org/W2127795505","https://openalex.org/W2139009001","https://openalex.org/W2146931154","https://openalex.org/W2149383870","https://openalex.org/W2149902802","https://openalex.org/W2150985363","https://openalex.org/W2151824694","https://openalex.org/W2154934646","https://openalex.org/W2157191248","https://openalex.org/W2162539355","https://openalex.org/W6682434072"],"related_works":["https://openalex.org/W2157212570","https://openalex.org/W2543176856","https://openalex.org/W2764440971","https://openalex.org/W1897203488","https://openalex.org/W2616892825","https://openalex.org/W1837475237","https://openalex.org/W2624668974","https://openalex.org/W3088373974","https://openalex.org/W2806771822","https://openalex.org/W2140497172"],"abstract_inverted_index":{"This":[0],"work":[1],"describes":[2],"an":[3,12],"optimized":[4],"DFT":[5,20],"architecture":[6],"and":[7,22,28],"its":[8],"implementation":[9],"strategy":[10],"for":[11],"Intel":[13],"high":[14,40],"performance":[15],"(>3":[16],"GHz)":[17],"microprocessor.":[18],"Major":[19],"features":[21],"ATPG":[23],"techniques":[24],"implemented":[25],"are":[26,31],"described":[27],"key":[29],"results":[30],"presented":[32],"to":[33],"show":[34],"the":[35,39],"return-on-investments":[36],"(ROI)":[37],"in":[38],"volume":[41],"manufacturing":[42],"(HVM)":[43],"test":[44],"environments.":[45]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}