{"id":"https://openalex.org/W1864835114","doi":"https://doi.org/10.1109/test.2002.1041933","title":"On-die DFT based solutions are sufficient for testing multi-GHz interfaces in manufacturing (and are also key to enabling lower cost ATE platforms)","display_name":"On-die DFT based solutions are sufficient for testing multi-GHz interfaces in manufacturing (and are also key to enabling lower cost ATE platforms)","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1864835114","doi":"https://doi.org/10.1109/test.2002.1041933","mag":"1864835114"},"language":"en","primary_location":{"id":"doi:10.1109/test.2002.1041933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041933","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113694745","display_name":"M. Tripp","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"M. Tripp","raw_affiliation_strings":["SorVTest Technology Development, Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"SorVTest Technology Development, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5113694745"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.3477,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.59632354,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1232","last_page":"1232"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chipset","display_name":"Chipset","score":0.9075911641120911},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8649001121520996},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.705428421497345},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5568985342979431},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5446353554725647},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5106976628303528},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4688872992992401},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42579036951065063},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40172243118286133},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2992117702960968},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12454432249069214},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10235863924026489},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.0877850353717804}],"concepts":[{"id":"https://openalex.org/C73431340","wikidata":"https://www.wikidata.org/wiki/Q182656","display_name":"Chipset","level":3,"score":0.9075911641120911},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8649001121520996},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.705428421497345},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5568985342979431},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5446353554725647},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5106976628303528},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4688872992992401},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42579036951065063},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40172243118286133},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2992117702960968},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12454432249069214},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10235863924026489},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0877850353717804},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2002.1041933","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041933","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2361454123","https://openalex.org/W2385247776","https://openalex.org/W2127916158","https://openalex.org/W2100196563","https://openalex.org/W2106546050","https://openalex.org/W2382142327","https://openalex.org/W2977359002","https://openalex.org/W2598933208","https://openalex.org/W2532282409","https://openalex.org/W2386515908"],"abstract_inverted_index":{"Based":[0],"on":[1,10,53],"experiences":[2],"with":[3],"500":[4],"MHz":[5],"to":[6,27],"1":[7],"GHz":[8],"interfaces":[9],"high":[11],"volume":[12],"CPU":[13],"and":[14,34,57],"chipset":[15],"products,":[16],"it":[17],"is":[18],"evident":[19],"that":[20],"on-die":[21],"DFT":[22,33],"based":[23],"solutions":[24],"are":[25],"sufficient":[26],"screen":[28],"defects":[29],"in":[30,42],"manufacturing.":[31],"On-die":[32],"test":[35],"methods":[36],"can":[37,63],"very":[38],"accurately":[39],"determine":[40],"differences":[41],"performance":[43],"(drive,":[44],"timing,":[45],"leakage,":[46],"jitter,...)":[47],"between":[48],"the":[49,58,61],"various":[50],"interface":[51],"channels":[52],"a":[54],"single":[55],"device,":[56],"magnitude":[59],"of":[60,68],"difference":[62],"be":[64],"used":[65],"as":[66],"indication":[67],"defective":[69],"channels.":[70]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}