{"id":"https://openalex.org/W2159152154","doi":"https://doi.org/10.1109/test.2002.1041899","title":"Position statement: TAPs all over my chips","display_name":"Position statement: TAPs all over my chips","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2159152154","doi":"https://doi.org/10.1109/test.2002.1041899","mag":"2159152154"},"language":"en","primary_location":{"id":"doi:10.1109/test.2002.1041899","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041899","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031569243","display_name":"S.F. Oakland","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S.F. Oakland","raw_affiliation_strings":["Microelectronics Division, IBM, Essex Junction, VT, USA"],"affiliations":[{"raw_affiliation_string":"Microelectronics Division, IBM, Essex Junction, VT, USA","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5031569243"],"corresponding_institution_ids":["https://openalex.org/I1341412227"],"apc_list":null,"apc_paid":null,"fwci":0.2515,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.58499756,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1192","last_page":"1192"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9883000254631042,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9883000254631042,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9613999724388123,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9574000239372253,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7613146305084229},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7591725587844849},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7275722026824951},{"id":"https://openalex.org/keywords/background-debug-mode-interface","display_name":"Background debug mode interface","score":0.6094424724578857},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5445953607559204},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5334491729736328},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5225562453269958},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4804382026195526},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4787173271179199},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.4173937141895294},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.31951314210891724},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1870458424091339},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09184679388999939},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08084556460380554}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7613146305084229},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7591725587844849},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7275722026824951},{"id":"https://openalex.org/C124774103","wikidata":"https://www.wikidata.org/wiki/Q4839640","display_name":"Background debug mode interface","level":3,"score":0.6094424724578857},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5445953607559204},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5334491729736328},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5225562453269958},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4804382026195526},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4787173271179199},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.4173937141895294},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.31951314210891724},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1870458424091339},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09184679388999939},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08084556460380554},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2002.1041899","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041899","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2361273971","https://openalex.org/W2351581202","https://openalex.org/W2978026406","https://openalex.org/W2385068581","https://openalex.org/W2381166695","https://openalex.org/W4241045879","https://openalex.org/W2366346238","https://openalex.org/W2388687068","https://openalex.org/W2366922255","https://openalex.org/W2387706296"],"abstract_inverted_index":{"Summary":[0],"form":[1],"only":[2],"given.":[3],"An":[4],"increasing":[5],"number":[6,81],"of":[7,58,73,79,82],"system-on-chip":[8],"(SoC)":[9],"application-specific":[10],"integrated":[11],"circuits":[12],"(ASICs)":[13],"have":[14],"more":[15],"than":[16],"one":[17,49],"embedded":[18,44,83],"processor":[19],"with":[20],"a":[21,30,34,41,51,54],"test":[22],"access":[23],"port":[24],"(TAP).":[25],"A":[26],"processor's":[27],"TAP":[28,56,64],"facilitates":[29],"hardware":[31],"interface":[32],"to":[33],"software":[35,75],"development/debug":[36],"tool.":[37],"The":[38],"author":[39],"presents":[40],"technique":[42],"whereby":[43],"TAPs":[45],"can":[46],"be":[47],"accessed":[48],"at":[50],"time":[52],"via":[53],"single":[55],"consisting":[57],"four":[59],"or":[60],"five":[61],"pins.":[62],"No":[63],"selection":[65],"pins":[66],"are":[67],"required,":[68],"and":[69],"the":[70,80],"runtime":[71],"performance":[72],"debug":[74],"is":[76],"relatively":[77],"independent":[78],"processors.":[84]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
