{"id":"https://openalex.org/W2149787624","doi":"https://doi.org/10.1109/test.2002.1041876","title":"Dedicated autonomous scan-based testing (DAST) for embedded cores","display_name":"Dedicated autonomous scan-based testing (DAST) for embedded cores","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2149787624","doi":"https://doi.org/10.1109/test.2002.1041876","mag":"2149787624"},"language":"en","primary_location":{"id":"doi:10.1109/test.2002.1041876","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041876","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084749652","display_name":"M. Nahvi","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"M. Nahvi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062724257","display_name":"A. Ivanov","orcid":"https://orcid.org/0000-0002-0882-6750"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"A. Ivanov","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111280120","display_name":"R. Saleh","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"R. Saleh","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5084749652"],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":0.9904,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.7767072,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1176","last_page":"1183"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9873999953269958,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7387732267379761},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6643512845039368},{"id":"https://openalex.org/keywords/hierarchy","display_name":"Hierarchy","score":0.543599009513855},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.517491340637207},{"id":"https://openalex.org/keywords/test-data","display_name":"Test data","score":0.4477425515651703},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.4418061375617981},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.41860896348953247},{"id":"https://openalex.org/keywords/integration-testing","display_name":"Integration testing","score":0.41778290271759033},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40472984313964844},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38472455739974976},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.23188182711601257},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23056596517562866},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.16873839497566223}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7387732267379761},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6643512845039368},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.543599009513855},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.517491340637207},{"id":"https://openalex.org/C16910744","wikidata":"https://www.wikidata.org/wiki/Q7705759","display_name":"Test data","level":2,"score":0.4477425515651703},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.4418061375617981},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.41860896348953247},{"id":"https://openalex.org/C107683887","wikidata":"https://www.wikidata.org/wiki/Q782466","display_name":"Integration testing","level":3,"score":0.41778290271759033},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40472984313964844},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38472455739974976},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.23188182711601257},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23056596517562866},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.16873839497566223},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/test.2002.1041876","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041876","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.118.828","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.118.828","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://soc.ece.ubc.ca/soc/publications/0041_3c.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W615030097","https://openalex.org/W1595368737","https://openalex.org/W1762004504","https://openalex.org/W1964811935","https://openalex.org/W2055927514","https://openalex.org/W2099502153","https://openalex.org/W2122955150","https://openalex.org/W2128038056","https://openalex.org/W2137171438","https://openalex.org/W2503952136","https://openalex.org/W4245308648"],"related_works":["https://openalex.org/W3142211975","https://openalex.org/W1879443270","https://openalex.org/W2018912978","https://openalex.org/W2130914040","https://openalex.org/W2119122672","https://openalex.org/W4292904049","https://openalex.org/W2136848245","https://openalex.org/W4213404769","https://openalex.org/W2118050502","https://openalex.org/W73562725"],"abstract_inverted_index":{"The":[0],"complexity":[1],"of":[2,26,43,93,100,109],"today's":[3],"chips":[4],"is":[5,14],"such":[6],"that":[7,36],"relying":[8],"solely":[9],"upon":[10],"external":[11],"ATE":[12,44,64,73],"resources":[13,45],"insufficient":[15],"for":[16,65],"scan":[17],"test.":[18],"In":[19],"this":[20],"work,":[21],"we":[22,70],"develop":[23],"the":[24,41,63],"concept":[25],"dedicated":[27,86],"autonomous":[28],"scan-based":[29],"testing":[30],"(DAST)":[31],"by":[32],"proposing":[33],"a":[34,107],"scheme":[35],"introduces":[37],"hierarchy":[38],"and":[39,54,59],"separates":[40],"functionality":[42],"into":[46],"two":[47],"distinctive":[48],"classes:":[49],"a)":[50],"test":[51,56,74],"data":[52,57,75],"communication,":[53],"b)":[55],"control":[58],"observation.":[60],"To":[61],"simplify":[62],"embedded":[66,91],"digital":[67],"core":[68],"testing,":[69],"propose":[71],"transferring":[72],"control/observation":[76],"functions":[77],"to":[78,87,106],"one":[79],"or":[80,89],"more":[81],"Embedded":[82],"Autonomous":[83],"Sequencers":[84],"(EAS)":[85],"single":[88],"multiple":[90],"cores":[92],"an":[94],"SoC":[95,110],"We":[96],"present":[97],"implementation":[98],"results":[99],"our":[101],"DAST":[102],"methodology":[103],"when":[104],"applied":[105],"number":[108],"benchmarks.":[111]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}