{"id":"https://openalex.org/W2115228544","doi":"https://doi.org/10.1109/test.2002.1041841","title":"Test setup simulation - a high-performance VHDL-based virtual test solution meeting industrial requirements","display_name":"Test setup simulation - a high-performance VHDL-based virtual test solution meeting industrial requirements","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2115228544","doi":"https://doi.org/10.1109/test.2002.1041841","mag":"2115228544"},"language":"en","primary_location":{"id":"doi:10.1109/test.2002.1041841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041841","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052885508","display_name":"G. Krampl","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":true,"raw_author_name":"G. Krampl","raw_affiliation_strings":["Infineon Technologies Microelectronic Design Centers Austria GmbH, Villach, Austria","Infineon Technol. Microelectron. Design Centers Austria GmbH, Villach, Austria"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies Microelectronic Design Centers Austria GmbH, Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]},{"raw_affiliation_string":"Infineon Technol. Microelectron. Design Centers Austria GmbH, Villach, Austria","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034217916","display_name":"M. Rona","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"M. Rona","raw_affiliation_strings":["Infineon Technologies Microelectronic Design Centers Austria GmbH, Villach, Austria","Infineon Technol. Microelectron. Design Centers Austria GmbH, Villach, Austria"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies Microelectronic Design Centers Austria GmbH, Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]},{"raw_affiliation_string":"Infineon Technol. Microelectron. Design Centers Austria GmbH, Villach, Austria","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033736849","display_name":"H. Tauber","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"H. Tauber","raw_affiliation_strings":["Infineon Technologies Microelectronic Design Centers Austria GmbH, Villach, Austria","Infineon Technol. Microelectron. Design Centers Austria GmbH, Villach, Austria"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies Microelectronic Design Centers Austria GmbH, Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]},{"raw_affiliation_string":"Infineon Technol. Microelectron. Design Centers Austria GmbH, Villach, Austria","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5052885508"],"corresponding_institution_ids":["https://openalex.org/I4210131793"],"apc_list":null,"apc_paid":null,"fwci":2.4535,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.89427687,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"870","last_page":"878"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8109561204910278},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7464800477027893},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.6454512476921082},{"id":"https://openalex.org/keywords/vhdl-ams","display_name":"VHDL-AMS","score":0.633965253829956},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.555793821811676},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.5403622984886169},{"id":"https://openalex.org/keywords/test-harness","display_name":"Test harness","score":0.5009968280792236},{"id":"https://openalex.org/keywords/device-under-test","display_name":"Device under test","score":0.4469517469406128},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4329086244106293},{"id":"https://openalex.org/keywords/test-management-approach","display_name":"Test Management Approach","score":0.4315706193447113},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.41317397356033325},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.40829864144325256},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36929798126220703},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.3013823628425598},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2713407278060913},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.1493247151374817}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8109561204910278},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7464800477027893},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.6454512476921082},{"id":"https://openalex.org/C2776513426","wikidata":"https://www.wikidata.org/wiki/Q2744740","display_name":"VHDL-AMS","level":4,"score":0.633965253829956},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.555793821811676},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5403622984886169},{"id":"https://openalex.org/C109852812","wikidata":"https://www.wikidata.org/wiki/Q2406355","display_name":"Test harness","level":5,"score":0.5009968280792236},{"id":"https://openalex.org/C76249512","wikidata":"https://www.wikidata.org/wiki/Q1206780","display_name":"Device under test","level":3,"score":0.4469517469406128},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4329086244106293},{"id":"https://openalex.org/C7435765","wikidata":"https://www.wikidata.org/wiki/Q7705776","display_name":"Test Management Approach","level":5,"score":0.4315706193447113},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.41317397356033325},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.40829864144325256},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36929798126220703},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3013823628425598},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2713407278060913},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.1493247151374817},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C44838205","wikidata":"https://www.wikidata.org/wiki/Q127995","display_name":"Microwave","level":2,"score":0.0},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2002.1041841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041841","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6399999856948853,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1893675745","https://openalex.org/W2102549045","https://openalex.org/W2154452044","https://openalex.org/W6998710840","https://openalex.org/W7034622842"],"related_works":["https://openalex.org/W1586741485","https://openalex.org/W1967668957","https://openalex.org/W2112319484","https://openalex.org/W2086925677","https://openalex.org/W2540912367","https://openalex.org/W2151941088","https://openalex.org/W2357636087","https://openalex.org/W2115181119","https://openalex.org/W2119440363","https://openalex.org/W3000216822"],"abstract_inverted_index":{"Virtual":[0],"test":[1,8,12,34,70,75],"(VT)":[2],"allows":[3],"the":[4,59,74],"debug":[5],"of":[6,58],"mixed-signal":[7],"programs":[9,35],"and":[10,23,28,67],"associated":[11],"hardware":[13,60],"in":[14],"a":[15,20,30,49,62,68,78,85],"simulation":[16],"environment":[17],"if":[18],"(1)":[19],"cheap,":[21],"fast":[22],"sufficiently":[24],"accurate":[25],"chip":[26],"model,":[27],"(2)":[29],"converter":[31],"software":[32],"linking":[33,73],"to":[36,77],"simulators":[37],"can":[38],"be":[39],"made":[40],"available.":[41],"This":[42],"paper":[43],"presents":[44],"TSS":[45],"(test":[46],"setup":[47],"simulation),":[48],"high-performance":[50],"VT":[51,82],"solution":[52],"based":[53],"on":[54],"pure":[55],"VHDL":[56],"modeling":[57],"involved,":[61],"VHDL-based":[63],"virtual":[64],"tester":[65],"concept":[66],"snapshot":[69],"data":[71],"extractor":[72],"program":[76],"simulator":[79],"together":[80],"with":[81],"results":[83],"for":[84],"complex":[86],"telecom":[87],"device.":[88]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
