{"id":"https://openalex.org/W2013221816","doi":"https://doi.org/10.1109/test.2002.1041782","title":"Testing cross-talk induced delay faults in static CMOS circuit through dynamic timing analysis","display_name":"Testing cross-talk induced delay faults in static CMOS circuit through dynamic timing analysis","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2013221816","doi":"https://doi.org/10.1109/test.2002.1041782","mag":"2013221816"},"language":"en","primary_location":{"id":"doi:10.1109/test.2002.1041782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111972172","display_name":"Bipul C. Paul","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"B.C. Paul","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031161187","display_name":"Kaushik Roy","orcid":"https://orcid.org/0009-0002-3375-2877"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Roy","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. engineering, Purdue Univ., West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5111972172"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":2.5154,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.89400877,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"384","last_page":"390"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.7049388885498047},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6578177213668823},{"id":"https://openalex.org/keywords/crosstalk","display_name":"Crosstalk","score":0.6505804061889648},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6465247273445129},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.584259569644928},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5536836981773376},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.530833899974823},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5061711668968201},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5061468482017517},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45215460658073425},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4381347894668579},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4283401072025299},{"id":"https://openalex.org/keywords/static-analysis","display_name":"Static analysis","score":0.4189968407154083},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4093005657196045},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.21711468696594238},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2083095908164978},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20032045245170593},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1353977620601654}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.7049388885498047},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6578177213668823},{"id":"https://openalex.org/C169822122","wikidata":"https://www.wikidata.org/wiki/Q230187","display_name":"Crosstalk","level":2,"score":0.6505804061889648},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6465247273445129},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.584259569644928},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5536836981773376},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.530833899974823},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5061711668968201},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5061468482017517},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45215460658073425},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4381347894668579},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4283401072025299},{"id":"https://openalex.org/C97686452","wikidata":"https://www.wikidata.org/wiki/Q7604153","display_name":"Static analysis","level":2,"score":0.4189968407154083},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4093005657196045},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.21711468696594238},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2083095908164978},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20032045245170593},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1353977620601654},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2002.1041782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16","score":0.7900000214576721}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1683546237","https://openalex.org/W1910575119","https://openalex.org/W2098706146","https://openalex.org/W2101267628","https://openalex.org/W2135694842","https://openalex.org/W2136753675","https://openalex.org/W2145750057","https://openalex.org/W2149107969","https://openalex.org/W2149396421","https://openalex.org/W2157160077","https://openalex.org/W2162523242","https://openalex.org/W2752885492","https://openalex.org/W6640160912","https://openalex.org/W6674918397","https://openalex.org/W7029321148"],"related_works":["https://openalex.org/W2100329931","https://openalex.org/W2094926594","https://openalex.org/W2357760762","https://openalex.org/W4235807419","https://openalex.org/W2167385408","https://openalex.org/W2145535176","https://openalex.org/W2158805860","https://openalex.org/W2144633290","https://openalex.org/W4246342274","https://openalex.org/W2029945169"],"abstract_inverted_index":{"In":[0,24],"deep":[1],"submicron":[2],"(DSM)":[3],"circuits":[4,87],"the":[5,19,51,77,84],"critical":[6,45],"path":[7],"obtained":[8],"from":[9],"static":[10],"timing":[11],"analysis":[12],"may":[13],"often":[14],"be":[15],"incorrect":[16],"due":[17],"to":[18,40,55,70,79,83],"significant":[20],"effect":[21],"of":[22,44,47],"crosstalk.":[23],"this":[25,91],"paper":[26],"we":[27],"present":[28],"a":[29,42,48,71],"new":[30],"algorithm":[31,62,92],"based":[32,63],"on":[33,64],"timed":[34],"automatic":[35],"test":[36],"pattern":[37],"generation":[38],"(ATPG)":[39],"generate":[41],"list":[43],"paths":[46,58],"circuit":[49],"and":[50,74,93],"corresponding":[52],"input":[53],"vectors":[54],"sensitize":[56],"these":[57],"under":[59],"cross-talk.":[60],"The":[61],"modified":[65],"PODEM":[66],"handles":[67],"multiple":[68],"aggressors":[69,78],"victim":[72],"node":[73],"properly":[75],"activates":[76],"obtain":[80],"maximum":[81],"coupling":[82],"victim.":[85],"Several":[86],"were":[88,95],"tested":[89],"using":[90],"results":[94],"verified":[96],"by":[97],"HSPICE":[98],"simulation.":[99]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
