{"id":"https://openalex.org/W1852743659","doi":"https://doi.org/10.1109/test.2002.1041781","title":"Analog macromodeling of capacitive coupling faults in digital circuit interconnects","display_name":"Analog macromodeling of capacitive coupling faults in digital circuit interconnects","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1852743659","doi":"https://doi.org/10.1109/test.2002.1041781","mag":"1852743659"},"language":"en","primary_location":{"id":"doi:10.1109/test.2002.1041781","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041781","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108376041","display_name":"A. Sathe","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A.D. Sathe","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020404037","display_name":"M.L. Bushnell","orcid":null},"institutions":[{"id":"https://openalex.org/I102322142","display_name":"Rutgers, The State University of New Jersey","ror":"https://ror.org/05vt9qd57","country_code":"US","type":"education","lineage":["https://openalex.org/I102322142"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.L. Bushnell","raw_affiliation_strings":["ECE Department, Rutgers University, Piscataway, NJ, USA"],"affiliations":[{"raw_affiliation_string":"ECE Department, Rutgers University, Piscataway, NJ, USA","institution_ids":["https://openalex.org/I102322142"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061066826","display_name":"V.D. Agrawal","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"V.D. Agrawal","raw_affiliation_strings":["Agere Systems, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Agere Systems, NJ, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5108376041"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":2.0123,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.86624452,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"375","last_page":"383"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.6277722716331482},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6130881309509277},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.582902193069458},{"id":"https://openalex.org/keywords/capacitive-coupling","display_name":"Capacitive coupling","score":0.5696618556976318},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5555397868156433},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5273205637931824},{"id":"https://openalex.org/keywords/coupling","display_name":"Coupling (piping)","score":0.5159952640533447},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.4807398319244385},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4572051167488098},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3684995770454407},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28538793325424194},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2649129033088684},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2123921513557434},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11631125211715698}],"concepts":[{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.6277722716331482},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6130881309509277},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.582902193069458},{"id":"https://openalex.org/C68278764","wikidata":"https://www.wikidata.org/wiki/Q444167","display_name":"Capacitive coupling","level":3,"score":0.5696618556976318},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5555397868156433},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5273205637931824},{"id":"https://openalex.org/C131584629","wikidata":"https://www.wikidata.org/wiki/Q4308705","display_name":"Coupling (piping)","level":2,"score":0.5159952640533447},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.4807398319244385},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4572051167488098},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3684995770454407},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28538793325424194},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2649129033088684},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2123921513557434},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11631125211715698},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2002.1041781","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041781","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1532220361","https://openalex.org/W1595368737","https://openalex.org/W1698480623","https://openalex.org/W1823801491","https://openalex.org/W1852743659","https://openalex.org/W1994241124","https://openalex.org/W2037037356","https://openalex.org/W2097811636","https://openalex.org/W2098706146","https://openalex.org/W2099405302","https://openalex.org/W2100783269","https://openalex.org/W2102075362","https://openalex.org/W2102181378","https://openalex.org/W2121190650","https://openalex.org/W2138086100","https://openalex.org/W2153410728","https://openalex.org/W2158485265","https://openalex.org/W4240408910","https://openalex.org/W4253397165","https://openalex.org/W6631578254","https://openalex.org/W6638244836","https://openalex.org/W6674918397","https://openalex.org/W6675143238","https://openalex.org/W6675620916","https://openalex.org/W6675629742","https://openalex.org/W6683203499"],"related_works":["https://openalex.org/W1494292626","https://openalex.org/W3217430545","https://openalex.org/W2083793411","https://openalex.org/W2088006178","https://openalex.org/W2069145203","https://openalex.org/W2108605716","https://openalex.org/W63550369","https://openalex.org/W1532891187","https://openalex.org/W2085176210","https://openalex.org/W4362719849"],"abstract_inverted_index":{"Proposes":[0],"a":[1,53],"new":[2,54],"analog":[3,9,27,94,109,116,121],"coupling":[4,48,87,143,147,171],"delay":[5],"fault":[6,34,112,148,172],"model":[7],"and":[8,39,71,74,98,105,160],"macromodeling":[10],"technique":[11],"to":[12,155,162],"generate":[13],"tests":[14],"for":[15,42,174],"these":[16],"faults.":[17,50],"To":[18],"our":[19],"knowledge,":[20],"this":[21],"is":[22,123],"the":[23,63,78,86,126,151,169],"first":[24,170],"time":[25],"that":[26],"macromodeling,":[28],"along":[29],"with":[30,139],"multiple-delay":[31],"sequential":[32,158,175],"digital":[33,43],"simulation,":[35,113],"using":[36],"differing":[37],"rise":[38],"fall":[40],"times":[41],"logic":[44],"gates,":[45],"effectively":[46],"detected":[47],"timing":[49],"We":[51],"propose":[52],"crosstalk":[55],"candidate":[56],"reduction":[57],"(CCR)":[58],"algorithm,":[59],"which":[60],"looks":[61],"at":[62],"entire":[64],"set":[65],"of":[66,125,153],"possible":[67],"signal":[68],"line":[69],"couplings":[70,76],"eliminates":[72],"impossible":[73],"uninteresting":[75],"from":[77],"final":[79],"list.":[80],"On":[81],"various":[82],"circuits,":[83,159],"CCR":[84],"reduced":[85],"candidates":[88],"by":[89],"98.1%,":[90],"on":[91,157,164],"average.":[92],"The":[93,120,133],"macromodels":[95,117],"eliminate":[96],"errors":[97],"uncertainty":[99],"about":[100],"whether":[101],"signals":[102],"actually":[103],"couple,":[104],"also":[106],"avoid":[107],"complete":[108],"simulation":[110],"during":[111],"as":[114],"all":[115],"are":[118,168],"precomputed.":[119],"macromodel":[122],"independent":[124],"circuit-under-test,":[127],"because":[128],"it":[129],"models":[130],"generalized":[131],"interconnect.":[132],"method":[134],"efficiently":[135],"handles":[136],"large":[137],"circuits":[138],"more":[140],"than":[141],"10,000":[142],"faults,":[144],"while":[145],"obtaining":[146],"coverages":[149],"in":[150],"range":[152],"4":[154],"10%":[156],"up":[161],"33%":[163],"combinational":[165],"circuits.":[166,176],"These":[167],"results":[173]},"counts_by_year":[{"year":2018,"cited_by_count":3},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}