{"id":"https://openalex.org/W2116182160","doi":"https://doi.org/10.1109/test.2002.1041778","title":"An integrated approach to yield loss characterization","display_name":"An integrated approach to yield loss characterization","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2116182160","doi":"https://doi.org/10.1109/test.2002.1041778","mag":"2116182160"},"language":"en","primary_location":{"id":"doi:10.1109/test.2002.1041778","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109071541","display_name":"M. Craig","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"M. Craig","raw_affiliation_strings":["Test Chip Division, HPL, Inc., Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Test Chip Division, HPL, Inc., Austin, TX, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088350530","display_name":"A. Jee","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. Jee","raw_affiliation_strings":["Design for Yield Division, HPL, Inc., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Design for Yield Division, HPL, Inc., San Jose, CA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082457874","display_name":"P. Maniar","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"P. Maniar","raw_affiliation_strings":["Design for Yield Division, HPL, Inc., San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Design for Yield Division, HPL, Inc., San Jose, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5109071541"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2515,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.55353142,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"350","last_page":"356"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/characterization","display_name":"Characterization (materials science)","score":0.717870831489563},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5895105004310608},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.575739860534668},{"id":"https://openalex.org/keywords/root-cause","display_name":"Root cause","score":0.5702268481254578},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.5421328544616699},{"id":"https://openalex.org/keywords/semiconductor-device-fabrication","display_name":"Semiconductor device fabrication","score":0.5207281708717346},{"id":"https://openalex.org/keywords/root-cause-analysis","display_name":"Root cause analysis","score":0.5088717937469482},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.46643900871276855},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4589918255805969},{"id":"https://openalex.org/keywords/process-design","display_name":"Process design","score":0.4432360827922821},{"id":"https://openalex.org/keywords/process-engineering","display_name":"Process engineering","score":0.374243825674057},{"id":"https://openalex.org/keywords/manufacturing-engineering","display_name":"Manufacturing engineering","score":0.3252038359642029},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28974878787994385},{"id":"https://openalex.org/keywords/process-integration","display_name":"Process integration","score":0.2615472674369812},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.2203262448310852},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.1372682750225067},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08955660462379456}],"concepts":[{"id":"https://openalex.org/C2780841128","wikidata":"https://www.wikidata.org/wiki/Q5073781","display_name":"Characterization (materials science)","level":2,"score":0.717870831489563},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5895105004310608},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.575739860534668},{"id":"https://openalex.org/C84945661","wikidata":"https://www.wikidata.org/wiki/Q7366567","display_name":"Root cause","level":2,"score":0.5702268481254578},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.5421328544616699},{"id":"https://openalex.org/C66018809","wikidata":"https://www.wikidata.org/wiki/Q1570432","display_name":"Semiconductor device fabrication","level":3,"score":0.5207281708717346},{"id":"https://openalex.org/C130963320","wikidata":"https://www.wikidata.org/wiki/Q1401207","display_name":"Root cause analysis","level":2,"score":0.5088717937469482},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.46643900871276855},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4589918255805969},{"id":"https://openalex.org/C55396564","wikidata":"https://www.wikidata.org/wiki/Q3084971","display_name":"Process design","level":3,"score":0.4432360827922821},{"id":"https://openalex.org/C21880701","wikidata":"https://www.wikidata.org/wiki/Q2144042","display_name":"Process engineering","level":1,"score":0.374243825674057},{"id":"https://openalex.org/C117671659","wikidata":"https://www.wikidata.org/wiki/Q11049265","display_name":"Manufacturing engineering","level":1,"score":0.3252038359642029},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28974878787994385},{"id":"https://openalex.org/C54725748","wikidata":"https://www.wikidata.org/wiki/Q7247277","display_name":"Process integration","level":2,"score":0.2615472674369812},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.2203262448310852},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.1372682750225067},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08955660462379456},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2002.1041778","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041778","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5400000214576721}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1957562125","https://openalex.org/W1967967217","https://openalex.org/W2098112833","https://openalex.org/W2181842310"],"related_works":["https://openalex.org/W2030594396","https://openalex.org/W2754538212","https://openalex.org/W3045668461","https://openalex.org/W2490884653","https://openalex.org/W4200610016","https://openalex.org/W4255366506","https://openalex.org/W2183996497","https://openalex.org/W2056250485","https://openalex.org/W129587375","https://openalex.org/W2799474201"],"abstract_inverted_index":{"Presents":[0],"an":[1],"integrated":[2],"approach":[3,53],"for":[4,13,26,39,47],"achieving":[5],"improved":[6],"yield":[7,59],"ramp":[8],"and":[9,33,42,45,61],"enhanced":[10],"manufacturing":[11,63],"margins":[12],"deep":[14],"sub-micron":[15],"process":[16,27],"technologies.":[17],"This":[18,52],"methodology":[19],"highlights":[20],"the":[21,36],"combination":[22],"of":[23,35],"design":[24,37],"IP":[25],"technology":[28],"characterization,":[29,41],"tailored":[30],"data":[31,40],"reduction":[32],"analysis":[34],"components":[38],"fault":[43],"modeling":[44],"extraction":[46],"root":[48],"cause":[49],"failure":[50],"determination.":[51],"enables":[54],"semiconductor":[55],"companies":[56],"to":[57],"characterize":[58],"loss":[60],"improve":[62],"process.":[64]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
