{"id":"https://openalex.org/W1792362277","doi":"https://doi.org/10.1109/test.2002.1041777","title":"Embedded memory test and repair: infrastructure IP for SOC yield","display_name":"Embedded memory test and repair: infrastructure IP for SOC yield","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W1792362277","doi":"https://doi.org/10.1109/test.2002.1041777","mag":"1792362277"},"language":"en","primary_location":{"id":"doi:10.1109/test.2002.1041777","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041777","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108606295","display_name":"Y. Zorian","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Y. Zorian","raw_affiliation_strings":["Virage Logic, Fremont, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Virage Logic, Fremont, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5108606295"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.9367,"has_fulltext":false,"cited_by_count":104,"citation_normalized_percentile":{"value":0.97155689,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"340","last_page":"349"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6260761618614197},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5874881148338318},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.5738246440887451},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5026094913482666}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6260761618614197},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5874881148338318},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.5738246440887451},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5026094913482666},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.2002.1041777","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.2002.1041777","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6499999761581421,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1922918362","https://openalex.org/W1967967217","https://openalex.org/W1985238821","https://openalex.org/W2046280094","https://openalex.org/W2054971791","https://openalex.org/W2096018418","https://openalex.org/W2098987953","https://openalex.org/W2101406832","https://openalex.org/W2104677646","https://openalex.org/W2122442616","https://openalex.org/W2134822007","https://openalex.org/W2148172069","https://openalex.org/W2154283179","https://openalex.org/W2156041716","https://openalex.org/W2163518473","https://openalex.org/W2171709948","https://openalex.org/W2503952136","https://openalex.org/W6675503376","https://openalex.org/W6679523228","https://openalex.org/W6682746215"],"related_works":["https://openalex.org/W2036806516","https://openalex.org/W1967394420","https://openalex.org/W2565425548","https://openalex.org/W2392009442","https://openalex.org/W13556768","https://openalex.org/W2100663632","https://openalex.org/W2154106283","https://openalex.org/W2912613323","https://openalex.org/W2031621863","https://openalex.org/W2353292666"],"abstract_inverted_index":{"Today's":[0],"system-on-chip":[1],"typically":[2],"embeds":[3],"memory":[4,23,65,80],"IP":[5,60,81,85,90],"cores":[6],"with":[7],"very":[8],"large":[9],"aggregate":[10],"bit":[11],"count":[12],"per":[13],"SoC.":[14],"This":[15,34],"trend":[16],"requires":[17],"using":[18],"dedicated":[19],"resources":[20],"to":[21,62,77],"increase":[22],"yield,":[24],"while":[25],"containing":[26],"test":[27],"and":[28,31,47,68,82],"repair":[29,56],"cost":[30],"minimizing":[32],"time-to-volume.":[33],"paper":[35],"summarizes":[36],"the":[37,55,64,69,79],"evolution":[38],"of":[39],"such":[40],"yield":[41],"optimization":[42],"resources,":[43],"compares":[44],"their":[45],"trade-offs,":[46],"concentrates":[48],"on":[49],"on-chip":[50],"infrastructure":[51,59,84],"IP.":[52],"To":[53],"maximize":[54],"efficiency,":[57],"this":[58],"needs":[61],"leverage":[63],"design":[66],"knowledge":[67],"process":[70],"failure":[71],"data.":[72],"The":[73],"ideal":[74],"solution":[75],"is":[76],"integrate":[78],"its":[83],"into":[86],"a":[87],"single":[88],"composite":[89],"that":[91],"yields":[92],"itself":[93],"effectively.":[94]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":9},{"year":2012,"cited_by_count":8}],"updated_date":"2026-05-06T08:25:59.206177","created_date":"2025-10-10T00:00:00"}