{"id":"https://openalex.org/W2158250981","doi":"https://doi.org/10.1109/test.1989.82382","title":"Cell-based test design method","display_name":"Cell-based test design method","publication_year":2003,"publication_date":"2003-01-13","ids":{"openalex":"https://openalex.org/W2158250981","doi":"https://doi.org/10.1109/test.1989.82382","mag":"2158250981"},"language":"en","primary_location":{"id":"doi:10.1109/test.1989.82382","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.1989.82382","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004839244","display_name":"Keiichi Sakashita","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Sakashita","raw_affiliation_strings":["LSI research and development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LSI research and development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113612012","display_name":"T. Hashizume","orcid":null},"institutions":[{"id":"https://openalex.org/I1306287861","display_name":"Mitsubishi Group (Japan)","ror":"https://ror.org/0234cd281","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Hashizume","raw_affiliation_strings":["Mitsubishi Electr. Corp., Hyogo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mitsubishi Electr. Corp., Hyogo, Japan","institution_ids":["https://openalex.org/I1306287861"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111964560","display_name":"Takeshi Ohya","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Ohya","raw_affiliation_strings":["LSI research and development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LSI research and development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063798001","display_name":"I. Takimoto","orcid":null},"institutions":[{"id":"https://openalex.org/I1306287861","display_name":"Mitsubishi Group (Japan)","ror":"https://ror.org/0234cd281","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"I. Takimoto","raw_affiliation_strings":["Mitsubishi Electr. Corp., Hyogo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mitsubishi Electr. Corp., Hyogo, Japan","institution_ids":["https://openalex.org/I1306287861"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063227191","display_name":"S. Kato","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Kato","raw_affiliation_strings":["LSI research and development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LSI research and development Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.24802179,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"909","last_page":"916"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7127693891525269},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.652060329914093},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6450185775756836},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.5845410227775574},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5676309466362},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.5606003403663635},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.5600552558898926},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5371392965316772},{"id":"https://openalex.org/keywords/test-vector","display_name":"Test vector","score":0.5312753915786743},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5101049542427063},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5037068724632263},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.47760602831840515},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.47166121006011963},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4592445194721222},{"id":"https://openalex.org/keywords/test-data","display_name":"Test data","score":0.42715984582901},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.41080546379089355},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3916865587234497},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3701006770133972},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3473414480686188},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.18335160613059998},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.16167470812797546},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1566714346408844},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1542089879512787},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.14556658267974854},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.11411711573600769}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7127693891525269},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.652060329914093},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6450185775756836},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.5845410227775574},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5676309466362},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.5606003403663635},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5600552558898926},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5371392965316772},{"id":"https://openalex.org/C100767440","wikidata":"https://www.wikidata.org/wiki/Q7705816","display_name":"Test vector","level":3,"score":0.5312753915786743},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5101049542427063},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5037068724632263},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.47760602831840515},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.47166121006011963},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4592445194721222},{"id":"https://openalex.org/C16910744","wikidata":"https://www.wikidata.org/wiki/Q7705759","display_name":"Test data","level":2,"score":0.42715984582901},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.41080546379089355},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3916865587234497},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3701006770133972},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3473414480686188},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.18335160613059998},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.16167470812797546},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1566714346408844},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1542089879512787},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.14556658267974854},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.11411711573600769},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/test.1989.82382","is_oa":false,"landing_page_url":"https://doi.org/10.1109/test.1989.82382","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 'Meeting the Tests of Time'., International Test Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1502206751","https://openalex.org/W1542564188","https://openalex.org/W2004437077","https://openalex.org/W2111134844","https://openalex.org/W2114313734","https://openalex.org/W2147185787","https://openalex.org/W2152633347","https://openalex.org/W4255275041","https://openalex.org/W6651354974"],"related_works":["https://openalex.org/W2125521459","https://openalex.org/W4245311057","https://openalex.org/W1588361197","https://openalex.org/W311918050","https://openalex.org/W2028462208","https://openalex.org/W2154529098","https://openalex.org/W2620614665","https://openalex.org/W2121466258","https://openalex.org/W2799101079","https://openalex.org/W2624668974"],"abstract_inverted_index":{"A":[0],"cell-based":[1,11],"test":[2,22,39,50,73,78,95,119],"design":[3,12,74],"method":[4],"which":[5,54,76],"is":[6,13,51],"consistent":[7],"with":[8,127],"features":[9],"of":[10,60,69,80,93,97,103,130],"introduced.":[14],"By":[15],"improving":[16],"shift":[17,44],"register":[18,45],"latches,":[19],"a":[20,38,42,47,71,98],"scan":[21,62],"for":[23,123],"asynchronous":[24],"circuits,":[25],"as":[26,28,85],"well":[27],"delay":[29],"tests":[30],"can":[31],"be":[32],"executed":[33],"effectively.":[34],"Also,":[35],"by":[36],"employing":[37],"bus":[40],"and":[41,88,102,106,115],"selector":[43],"configuration,":[46],"multiple":[48],"scan-path":[49],"realized":[52],"attractively,":[53],"drastically":[55],"reduces":[56],"the":[57,61,67,77,91,94,104,112,116,128],"execution":[58],"time":[59,120],"test.":[63],"This":[64],"results":[65],"in":[66,75,90,118],"possibility":[68],"realizing":[70],"hierarchical":[72],"vectors":[79],"module":[81],"circuits":[82],"are":[83,121],"saved":[84],"library":[86],"data":[87],"used":[89],"preparation":[92],"vector":[96],"newly":[99],"developed":[100],"chip":[101],"schematic":[105],"artwork":[107],"data.":[108],"It":[109],"appears":[110],"that":[111],"area":[113],"overhead":[114],"increase":[117],"reasonable":[122],"future":[124],"VLSI":[125],"chips":[126],"complexity":[129],"1M":[131],"transistors.>":[132]},"counts_by_year":[],"updated_date":"2026-07-31T08:31:51.225901","created_date":"2025-10-10T00:00:00"}