{"id":"https://openalex.org/W7130393462","doi":"https://doi.org/10.1109/tencon66050.2025.11374934","title":"Development of High-Performance Multiply-Accumulate (Mac) Unit Design on Fpga for DSP Applications","display_name":"Development of High-Performance Multiply-Accumulate (Mac) Unit Design on Fpga for DSP Applications","publication_year":2025,"publication_date":"2025-10-27","ids":{"openalex":"https://openalex.org/W7130393462","doi":"https://doi.org/10.1109/tencon66050.2025.11374934"},"language":null,"primary_location":{"id":"doi:10.1109/tencon66050.2025.11374934","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tencon66050.2025.11374934","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"TENCON 2025 - 2025 IEEE Region 10 Conference (TENCON)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5126280781","display_name":"Nazirul Hafiz Mohd Nazeri","orcid":null},"institutions":[{"id":"https://openalex.org/I4210115733","display_name":"Penang Development Corporation","ror":"https://ror.org/02255bn64","country_code":"MY","type":"government","lineage":["https://openalex.org/I4210115733"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Nazirul Hafiz Mohd Nazeri","raw_affiliation_strings":["Sophic Automation Sdn Bhd,Bayan Lepas,Penang,Malaysia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sophic Automation Sdn Bhd,Bayan Lepas,Penang,Malaysia","institution_ids":["https://openalex.org/I4210115733"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018507037","display_name":"Siti Zarina Md Naziri","orcid":null},"institutions":[{"id":"https://openalex.org/I65079550","display_name":"Universiti Malaysia Perlis","ror":"https://ror.org/00xmkb790","country_code":"MY","type":"education","lineage":["https://openalex.org/I65079550"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Siti Zarina Md Naziri","raw_affiliation_strings":["Universiti Malaysia Perlis,Faculty of Electronic Engineering & Technology,Arau,Perlis,Malaysia,02600"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universiti Malaysia Perlis,Faculty of Electronic Engineering & Technology,Arau,Perlis,Malaysia,02600","institution_ids":["https://openalex.org/I65079550"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053483704","display_name":"Rizalafande Che Ismail","orcid":"https://orcid.org/0000-0002-2379-6115"},"institutions":[{"id":"https://openalex.org/I65079550","display_name":"Universiti Malaysia Perlis","ror":"https://ror.org/00xmkb790","country_code":"MY","type":"education","lineage":["https://openalex.org/I65079550"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Rizalafande Che Ismail","raw_affiliation_strings":["Universiti Malaysia Perlis,Faculty of Electronic Engineering & Technology,Arau,Perlis,Malaysia,02600"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universiti Malaysia Perlis,Faculty of Electronic Engineering & Technology,Arau,Perlis,Malaysia,02600","institution_ids":["https://openalex.org/I65079550"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.70798057,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"248","last_page":"252"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.935699999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.935699999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.011500000022351742,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.006000000052154064,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9150999784469604},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.6272000074386597},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6067000031471252},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.604200005531311},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5935999751091003},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.553600013256073},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5493000149726868},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.5273000001907349},{"id":"https://openalex.org/keywords/booths-multiplication-algorithm","display_name":"Booth's multiplication algorithm","score":0.5170000195503235}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9150999784469604},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6908000111579895},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.6272000074386597},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6067000031471252},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.604200005531311},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5935999751091003},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5843999981880188},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.553600013256073},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5493000149726868},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.5273000001907349},{"id":"https://openalex.org/C72475854","wikidata":"https://www.wikidata.org/wiki/Q477049","display_name":"Booth's multiplication algorithm","level":4,"score":0.5170000195503235},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.46560001373291016},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.43939998745918274},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38940000534057617},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.36500000953674316},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.31839999556541443},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3149000108242035},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3116999864578247},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.29429998993873596},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.27799999713897705},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.2734000086784363},{"id":"https://openalex.org/C75695347","wikidata":"https://www.wikidata.org/wiki/Q225147","display_name":"32-bit","level":2,"score":0.2705000042915344},{"id":"https://openalex.org/C33652231","wikidata":"https://www.wikidata.org/wiki/Q194368","display_name":"16-bit","level":2,"score":0.27000001072883606},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.26930001378059387},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.2671000063419342},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2606000006198883},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.2529999911785126}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tencon66050.2025.11374934","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tencon66050.2025.11374934","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"TENCON 2025 - 2025 IEEE Region 10 Conference (TENCON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7749056220054626,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W3014822860","https://openalex.org/W3037712939","https://openalex.org/W4206624696","https://openalex.org/W4308197794","https://openalex.org/W4381465310","https://openalex.org/W4392400256","https://openalex.org/W4401387029","https://openalex.org/W4405358685","https://openalex.org/W4406729457","https://openalex.org/W4407837505","https://openalex.org/W4408258312","https://openalex.org/W4408258494","https://openalex.org/W4410013755"],"related_works":[],"abstract_inverted_index":{"The":[0,73,89,109,129,140,184],"multiply-accumulate":[1],"(MAC)":[2],"unit":[3,81,111,202],"performs":[4],"multiplication":[5],"and":[6,43,54,58,69,99,117,123,162,195],"accumulation,":[7],"which":[8,103],"makes":[9],"it":[10],"an":[11,78,155],"essential":[12],"component":[13],"for":[14,26],"digital":[15],"signal":[16],"processing":[17],"(DSP)":[18],"applications.":[19],"Designing":[20],"high-performance":[21],"MAC":[22,80,110,201],"units":[23],"is":[24,112],"crucial":[25],"enhancing":[27],"the":[28,134,145,172,189],"computational":[29],"efficiency":[30],"of":[31,86,152,158,167],"modern":[32],"computer":[33],"systems.":[34],"However,":[35],"achieving":[36],"a":[37,47,93,149,163],"balance":[38],"between":[39],"delay,":[40],"power":[41,165],"consumption,":[42],"area":[44,156],"utilization":[45,157],"poses":[46],"significant":[48],"challenge.":[49],"This":[50],"study":[51,185],"thoroughly":[52],"compares":[53],"analyzes":[55],"various":[56],"multiplier":[57,191],"adder":[59,98,102,194,198],"architectures,":[60],"including":[61],"Vedic":[62,94,190],"multipliers,":[63],"ripple":[64],"carry":[65],"adders,":[66],"Brent-Kung":[67,97,101,193],"adders":[68],"pipelined":[70],"BrentKung":[71,197],"adders.":[72],"research":[74],"aims":[75],"to":[76],"design":[77,91,130,147],"efficient":[79],"by":[82],"investigating":[83],"optimal":[84],"combinations":[85],"these":[87],"components.":[88],"proposed":[90,146],"utilizes":[92],"Multiplier":[95],"using":[96,119,126],"Pipeline":[100,196],"are":[104],"compared":[105],"with":[106,192],"other":[107],"configurations.":[108],"implemented":[113,132],"in":[114,171],"Verilog":[115],"HDL":[116],"analyzed":[118],"Intel":[120,127],"Quartus":[121],"Prime":[122],"functionally":[124],"verified":[125],"ModelSim.":[128],"was":[131],"on":[133],"Altera":[135],"Cyclone":[136],"V":[137],"5CSXFC6D6F31I7ES":[138],"FPGA.":[139],"synthesis":[141],"process":[142],"reveals":[143],"that":[144,187],"achieves":[148],"low":[150],"delay":[151],"28.506":[153],"ns,":[154],"360":[159],"LUT":[160],"units,":[161],"balanced":[164],"consumption":[166],"427.600":[168],"mW,":[169],"resulting":[170],"speed":[173],"of$\\mathbf{3":[174],"1":[175],"0.":[176],"8":[177],"5":[178],"0":[179],"~":[180],"M":[181],"H":[182],"z}$.":[183],"concludes":[186],"combining":[188],"significantly":[199],"improves":[200],"performance.":[203]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2026-02-19T00:00:00"}