{"id":"https://openalex.org/W4388894605","doi":"https://doi.org/10.1109/tencon58879.2023.10322483","title":"A Layout Area Reduction of Basic Logic Element by Using a Neuron CMOS Type 4-input Variable Logic Circuit","display_name":"A Layout Area Reduction of Basic Logic Element by Using a Neuron CMOS Type 4-input Variable Logic Circuit","publication_year":2023,"publication_date":"2023-10-31","ids":{"openalex":"https://openalex.org/W4388894605","doi":"https://doi.org/10.1109/tencon58879.2023.10322483"},"language":"en","primary_location":{"id":"doi:10.1109/tencon58879.2023.10322483","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/tencon58879.2023.10322483","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"TENCON 2023 - 2023 IEEE Region 10 Conference (TENCON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101374202","display_name":"Shoma Ito","orcid":null},"institutions":[{"id":"https://openalex.org/I1314466530","display_name":"Tokai University","ror":"https://ror.org/01p7qe739","country_code":"JP","type":"education","lineage":["https://openalex.org/I1314466530"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shoma Ito","raw_affiliation_strings":["Graduate School of Information and Telecommunication Engineering, Tokai University,Tokyo,Japan","Graduate School of Information and Telecommunication Engineering, Tokai University, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information and Telecommunication Engineering, Tokai University,Tokyo,Japan","institution_ids":["https://openalex.org/I1314466530"]},{"raw_affiliation_string":"Graduate School of Information and Telecommunication Engineering, Tokai University, Tokyo, Japan","institution_ids":["https://openalex.org/I1314466530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109657586","display_name":"Hisaya Sawada","orcid":null},"institutions":[{"id":"https://openalex.org/I1314466530","display_name":"Tokai University","ror":"https://ror.org/01p7qe739","country_code":"JP","type":"education","lineage":["https://openalex.org/I1314466530"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hisaya Sawada","raw_affiliation_strings":["Graduate School of Information and Telecommunication Engineering, Tokai University,Tokyo,Japan","Graduate School of Information and Telecommunication Engineering, Tokai University, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information and Telecommunication Engineering, Tokai University,Tokyo,Japan","institution_ids":["https://openalex.org/I1314466530"]},{"raw_affiliation_string":"Graduate School of Information and Telecommunication Engineering, Tokai University, Tokyo, Japan","institution_ids":["https://openalex.org/I1314466530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113622884","display_name":"Hirotaka Furukawa","orcid":null},"institutions":[{"id":"https://openalex.org/I1314466530","display_name":"Tokai University","ror":"https://ror.org/01p7qe739","country_code":"JP","type":"education","lineage":["https://openalex.org/I1314466530"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hirotaka Furukawa","raw_affiliation_strings":["School of Information Telecommunication Engineering, Tokai University,Department of Embedded Technology,Tokyo,Japan","Department of Embedded Technology, School of Information Telecommunication Engineering, Tokai University, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Information Telecommunication Engineering, Tokai University,Department of Embedded Technology,Tokyo,Japan","institution_ids":["https://openalex.org/I1314466530"]},{"raw_affiliation_string":"Department of Embedded Technology, School of Information Telecommunication Engineering, Tokai University, Tokyo, Japan","institution_ids":["https://openalex.org/I1314466530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093314814","display_name":"Naruaki Hokari","orcid":null},"institutions":[{"id":"https://openalex.org/I1314466530","display_name":"Tokai University","ror":"https://ror.org/01p7qe739","country_code":"JP","type":"education","lineage":["https://openalex.org/I1314466530"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Naruaki Hokari","raw_affiliation_strings":["School of Information Telecommunication Engineering, Tokai University,Department of Embedded Technology,Tokyo,Japan","Department of Embedded Technology, School of Information Telecommunication Engineering, Tokai University, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Information Telecommunication Engineering, Tokai University,Department of Embedded Technology,Tokyo,Japan","institution_ids":["https://openalex.org/I1314466530"]},{"raw_affiliation_string":"Department of Embedded Technology, School of Information Telecommunication Engineering, Tokai University, Tokyo, Japan","institution_ids":["https://openalex.org/I1314466530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021738873","display_name":"Daishi Nishiguchi","orcid":null},"institutions":[{"id":"https://openalex.org/I97663771","display_name":"Kyushu Tokai University","ror":"https://ror.org/00w0f8567","country_code":"JP","type":"education","lineage":["https://openalex.org/I97663771"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Daishi Nishiguchi","raw_affiliation_strings":["Research Institute of Science and Technology, Tokai University,Kumamoto,Japan","Research Institute of Science and Technology, Tokai University, Kumamoto, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Research Institute of Science and Technology, Tokai University,Kumamoto,Japan","institution_ids":["https://openalex.org/I97663771"]},{"raw_affiliation_string":"Research Institute of Science and Technology, Tokai University, Kumamoto, Japan","institution_ids":["https://openalex.org/I97663771"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111367761","display_name":"Masaaki Fukuhara","orcid":null},"institutions":[{"id":"https://openalex.org/I1314466530","display_name":"Tokai University","ror":"https://ror.org/01p7qe739","country_code":"JP","type":"education","lineage":["https://openalex.org/I1314466530"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masaaki Fukuhara","raw_affiliation_strings":["Graduate School of Information and Telecommunication Engineering, Tokai University,Tokyo,Japan","Graduate School of Information and Telecommunication Engineering, Tokai University, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information and Telecommunication Engineering, Tokai University,Tokyo,Japan","institution_ids":["https://openalex.org/I1314466530"]},{"raw_affiliation_string":"Graduate School of Information and Telecommunication Engineering, Tokai University, Tokyo, Japan","institution_ids":["https://openalex.org/I1314466530"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13950984,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"J86-C","issue":null,"first_page":"564","last_page":"569"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6044759750366211},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5727376937866211},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5386512279510498},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.537085235118866},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5282912254333496},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5247542858123779},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5211853384971619},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.4888305068016052},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.48143598437309265},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.48140883445739746},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.48099076747894287},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4651672840118408},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45364829897880554},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4167083501815796},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31468820571899414},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.28295832872390747},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.26844465732574463},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.241116464138031},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2071448266506195},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18211379647254944},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17906367778778076}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6044759750366211},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5727376937866211},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5386512279510498},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.537085235118866},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5282912254333496},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5247542858123779},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5211853384971619},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.4888305068016052},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.48143598437309265},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.48140883445739746},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.48099076747894287},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4651672840118408},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45364829897880554},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4167083501815796},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31468820571899414},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.28295832872390747},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.26844465732574463},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.241116464138031},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2071448266506195},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18211379647254944},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17906367778778076},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tencon58879.2023.10322483","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/tencon58879.2023.10322483","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"TENCON 2023 - 2023 IEEE Region 10 Conference (TENCON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.47999998927116394}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1983051814","https://openalex.org/W2160142098","https://openalex.org/W3160639767"],"related_works":["https://openalex.org/W3105918491","https://openalex.org/W2789662562","https://openalex.org/W2525933112","https://openalex.org/W2197466303","https://openalex.org/W2490069675","https://openalex.org/W2102777336","https://openalex.org/W1905312773","https://openalex.org/W2139569078","https://openalex.org/W2103473573","https://openalex.org/W2170504327"],"abstract_inverted_index":{"As":[0],"Field":[1],"Programmable":[2],"Gate":[3],"Arrays":[4],"(FPGAs)":[5],"become":[6],"large":[7],"integration,":[8],"the":[9,64,72,80,83,87,106,111],"area":[10,108],"reduction":[11],"of":[12,82,100],"a":[13,20,23,33,46,57,98],"Basic":[14],"Logic":[15,35,49],"Element":[16],"(BLE),":[17],"which":[18],"is":[19,28],"circuit":[21,55,61],"for":[22],"logical":[24],"definition":[25],"in":[26,63,91],"FPGAs,":[27],"required.":[29],"We":[30],"have":[31,44],"studied":[32],"Variable":[34,48],"Circuit":[36,50],"(vVLC)":[37],"using":[38,102],"neuron":[39],"CMOS":[40],"inverters":[41],"(vCMOSs)":[42],"and":[43,75,77,86,109,113],"proposed":[45],"4-input":[47,58],"(4-vVLC)":[51],"as":[52],"an":[53],"alternative":[54],"against":[56],"Look-Up":[59],"Table":[60],"(4-LUT)":[62],"ordinary":[65],"BLE.":[66],"In":[67,94],"this":[68],"paper,":[69],"we":[70,96],"describe":[71],"4-vVLC":[73,103],"configuration":[74],"operations,":[76],"verify":[78],"that":[79],"results":[81],"HSPICE":[84],"simulations":[85],"theoretical":[88],"performances":[89],"are":[90],"general":[92],"agreement.":[93],"addition,":[95],"design":[97],"layout":[99],"BLEs":[101],"to":[104],"reduce":[105],"BLE":[107],"compare":[110],"4-LUT":[112],"4-vVLC.":[114]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
