{"id":"https://openalex.org/W4388894627","doi":"https://doi.org/10.1109/tencon58879.2023.10322338","title":"A Design of Low Voltage Spacer Detector Circuits for Asynchronous Ternary Logic System","display_name":"A Design of Low Voltage Spacer Detector Circuits for Asynchronous Ternary Logic System","publication_year":2023,"publication_date":"2023-10-31","ids":{"openalex":"https://openalex.org/W4388894627","doi":"https://doi.org/10.1109/tencon58879.2023.10322338"},"language":"en","primary_location":{"id":"doi:10.1109/tencon58879.2023.10322338","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/tencon58879.2023.10322338","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"TENCON 2023 - 2023 IEEE Region 10 Conference (TENCON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057624696","display_name":"Pitchayapatchaya Srikram","orcid":null},"institutions":[{"id":"https://openalex.org/I10245363","display_name":"Rajamangala University of Technology","ror":"https://ror.org/051qqcg15","country_code":"TH","type":"education","lineage":["https://openalex.org/I10245363"]}],"countries":["TH"],"is_corresponding":false,"raw_author_name":"Pitchayapatchaya Srikram","raw_affiliation_strings":["Rajamangala University of Technology Thanyaburi,dept. computer engineering,Pathum thani,Thailand","dept. computer engineering, Rajamangala University of Technology Thanyaburi, Pathum thani, Thailand"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Rajamangala University of Technology Thanyaburi,dept. computer engineering,Pathum thani,Thailand","institution_ids":["https://openalex.org/I10245363"]},{"raw_affiliation_string":"dept. computer engineering, Rajamangala University of Technology Thanyaburi, Pathum thani, Thailand","institution_ids":["https://openalex.org/I10245363"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046259966","display_name":"Thanasin Bunnam","orcid":"https://orcid.org/0000-0002-5014-6441"},"institutions":[{"id":"https://openalex.org/I10245363","display_name":"Rajamangala University of Technology","ror":"https://ror.org/051qqcg15","country_code":"TH","type":"education","lineage":["https://openalex.org/I10245363"]}],"countries":["TH"],"is_corresponding":false,"raw_author_name":"Thanasin Bunnam","raw_affiliation_strings":["Rajamangala University of Technology Thanyaburi,dept. computer engineering,Pathum thani,Thailand","dept. computer engineering, Rajamangala University of Technology Thanyaburi, Pathum thani, Thailand"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Rajamangala University of Technology Thanyaburi,dept. computer engineering,Pathum thani,Thailand","institution_ids":["https://openalex.org/I10245363"]},{"raw_affiliation_string":"dept. computer engineering, Rajamangala University of Technology Thanyaburi, Pathum thani, Thailand","institution_ids":["https://openalex.org/I10245363"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13951391,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"460","last_page":"463"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.6490797996520996},{"id":"https://openalex.org/keywords/pull-up-resistor","display_name":"Pull-up resistor","score":0.6281944513320923},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5972439050674438},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5721067786216736},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5332804322242737},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5284863710403442},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.5067818760871887},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4975610077381134},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4861557185649872},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.47629275918006897},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4760536849498749},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4667622745037079},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43875420093536377},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28503328561782837},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.1049346923828125}],"concepts":[{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.6490797996520996},{"id":"https://openalex.org/C61818909","wikidata":"https://www.wikidata.org/wiki/Q1987617","display_name":"Pull-up resistor","level":5,"score":0.6281944513320923},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5972439050674438},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5721067786216736},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5332804322242737},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5284863710403442},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.5067818760871887},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4975610077381134},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4861557185649872},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.47629275918006897},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4760536849498749},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4667622745037079},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43875420093536377},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28503328561782837},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.1049346923828125},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tencon58879.2023.10322338","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/tencon58879.2023.10322338","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"TENCON 2023 - 2023 IEEE Region 10 Conference (TENCON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8799999952316284,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W187479963","https://openalex.org/W1500308508","https://openalex.org/W1879553245","https://openalex.org/W2091193152","https://openalex.org/W2109124660","https://openalex.org/W2124772847","https://openalex.org/W2552019093","https://openalex.org/W3128997945","https://openalex.org/W3184548748","https://openalex.org/W6607757538","https://openalex.org/W6630479723","https://openalex.org/W6703978667"],"related_works":["https://openalex.org/W2171566066","https://openalex.org/W2114346412","https://openalex.org/W2580743037","https://openalex.org/W127821896","https://openalex.org/W2152533674","https://openalex.org/W2100080062","https://openalex.org/W2127519131","https://openalex.org/W1593138522","https://openalex.org/W2122938731","https://openalex.org/W3080459857"],"abstract_inverted_index":{"The":[0,45,145],"ternary":[1,31],"logic":[2,23,32,54],"approach":[3],"was":[4,110,148],"proposed":[5,129,146],"in":[6,18,30,150,157,171],"an":[7],"asynchronous":[8,52],"digital":[9],"system":[10],"to":[11,20,33,43,60,70,95,122,176],"eliminate":[12],"overhead":[13],"wires":[14],"for":[15,56],"communication":[16],"signals":[17],"preference":[19],"the":[21,38,85,88,93,97,117,158,169],"binary":[22],"approach.":[24],"Spacer":[25],"detectors":[26],"(SDs)":[27],"are":[28,67],"crucial":[29],"determine":[34,96],"whether":[35],"or":[36,77],"not":[37],"input":[39],"voltage":[40,83,137,173],"is":[41],"equivalent":[42],"empty.":[44],"Internet":[46],"of":[47,87,92,116],"Things":[48],"(IoT)":[49],"devices":[50,66],"leverage":[51],"multi-value":[53],"systems":[55],"machine":[57],"learning":[58],"inference":[59],"minimize":[61],"power":[62,165],"consumption.":[63],"These":[64],"IoT":[65],"also":[68],"expected":[69],"operate":[71,133],"at":[72,134],"ultra-low":[73,81],"operating":[74],"voltages":[75],"(sub-":[76],"near-threshold":[78],"voltages).":[79],"An":[80],"supply":[82,136,172],"restricts":[84],"operation":[86],"SD":[89,108,130],"circuit":[90,121,147],"because":[91],"need":[94],"space":[98],"value":[99],"with":[100,164,168],"a":[101,112,142],"logical":[102],"intermediate":[103],"value.":[104],"This":[105],"study":[106],"presented":[107],"circuits":[109,131],"applied":[111],"pseudodifferential":[113],"amplifier":[114],"instead":[115],"traditional":[118],"element-based":[119],"inverter":[120],"design":[123,162],"H-element":[124],"and":[125],"L-element.":[126],"Hence,":[127],"our":[128],"can":[132],"low":[135],"without":[138],"body":[139],"bias":[140],"using":[141],"bulk-controlled":[143],"method.":[144],"simulated":[149],"65":[151],"nm":[152],"UMC":[153],"LL":[154],"process":[155],"technology":[156],"Cadence":[159],"Virtuoso":[160],"analogue":[161],"environment":[163],"consumption":[166],"compared":[167],"difference":[170],"from":[174],"0.35":[175],"0.9":[177],"volts.":[178]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
