{"id":"https://openalex.org/W7117484801","doi":"https://doi.org/10.1109/te.2025.3646934","title":"CliCFPGA: Leveraging FPGA Education and Research Through Collaborative and Low-Code Heterogeneous Platform","display_name":"CliCFPGA: Leveraging FPGA Education and Research Through Collaborative and Low-Code Heterogeneous Platform","publication_year":2025,"publication_date":"2025-12-29","ids":{"openalex":"https://openalex.org/W7117484801","doi":"https://doi.org/10.1109/te.2025.3646934"},"language":null,"primary_location":{"id":"doi:10.1109/te.2025.3646934","is_oa":false,"landing_page_url":"https://doi.org/10.1109/te.2025.3646934","pdf_url":null,"source":{"id":"https://openalex.org/S207741693","display_name":"IEEE Transactions on Education","issn_l":"0018-9359","issn":["0018-9359","1557-9638"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310322189","host_organization_name":"IEEE Education Society","host_organization_lineage":["https://openalex.org/P4310322189","https://openalex.org/P4310319808"],"host_organization_lineage_names":["IEEE Education Society","Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Education","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001944273","display_name":"Rashed Al Amin","orcid":null},"institutions":[{"id":"https://openalex.org/I206895457","display_name":"University of Siegen","ror":"https://ror.org/02azyry73","country_code":"DE","type":"education","lineage":["https://openalex.org/I206895457"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rashed Al Amin","raw_affiliation_strings":["Institute for Embedded Systems, University of Siegen, Siegen, Germany"],"raw_orcid":"https://orcid.org/0000-0001-7237-6240","affiliations":[{"raw_affiliation_string":"Institute for Embedded Systems, University of Siegen, Siegen, Germany","institution_ids":["https://openalex.org/I206895457"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5121505931","display_name":"Roman Obermaisser","orcid":null},"institutions":[{"id":"https://openalex.org/I206895457","display_name":"University of Siegen","ror":"https://ror.org/02azyry73","country_code":"DE","type":"education","lineage":["https://openalex.org/I206895457"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Roman Obermaisser","raw_affiliation_strings":["Institute for Embedded Systems, University of Siegen, Siegen, Germany"],"raw_orcid":"https://orcid.org/0009-0002-4483-1503","affiliations":[{"raw_affiliation_string":"Institute for Embedded Systems, University of Siegen, Siegen, Germany","institution_ids":["https://openalex.org/I206895457"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I206895457"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.57814388,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"69","issue":"1","first_page":"19","last_page":"30"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.7105000019073486,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.7105000019073486,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.11959999799728394,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.06369999796152115,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8324999809265137},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.5756999850273132},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5212000012397766},{"id":"https://openalex.org/keywords/workspace","display_name":"Workspace","score":0.47870001196861267},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4458000063896179},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4185999929904938},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.39079999923706055},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.33889999985694885}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8324999809265137},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7483999729156494},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5777999758720398},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5756999850273132},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5212000012397766},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5045999884605408},{"id":"https://openalex.org/C58581272","wikidata":"https://www.wikidata.org/wiki/Q12741163","display_name":"Workspace","level":3,"score":0.47870001196861267},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4458000063896179},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4185999929904938},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.39079999923706055},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38679999113082886},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.33889999985694885},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.3151000142097473},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.3122999966144562},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.30410000681877136},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.28189998865127563},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.2815000116825104},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.2754000127315521},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.2621999979019165},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.2524000108242035},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.25220000743865967}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/te.2025.3646934","is_oa":false,"landing_page_url":"https://doi.org/10.1109/te.2025.3646934","pdf_url":null,"source":{"id":"https://openalex.org/S207741693","display_name":"IEEE Transactions on Education","issn_l":"0018-9359","issn":["0018-9359","1557-9638"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310322189","host_organization_name":"IEEE Education Society","host_organization_lineage":["https://openalex.org/P4310322189","https://openalex.org/P4310319808"],"host_organization_lineage_names":["IEEE Education Society","Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Education","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.508807361125946,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"The":[0],"rising":[1],"demand":[2],"for":[3,41,44,65,166,216,231],"real-time":[4,125],"data":[5],"processing":[6,28],"has":[7],"made":[8],"field":[9],"programmable":[10,15],"gate":[11],"arrays":[12],"(FPGAs)":[13],"essential":[14],"accelerators,":[16],"offering":[17],"superior":[18],"performance":[19,191],"and":[20,26,57,63,87,104,116,133,140,168,190,205,220,235,243,248],"lower":[21],"power":[22],"consumption":[23],"than":[24],"microprocessors":[25],"graphics":[27],"units":[29],"(GPUs).":[30],"However,":[31],"FPGA":[32,52,84,130,233],"development":[33],"environments":[34],"present":[35],"several":[36],"challenges,":[37],"including":[38],"the":[39,68,142,194,217],"need":[40],"high-end":[42],"computers":[43],"faster":[45,203],"hardware":[46,114,152,170],"compilation,":[47],"managing":[48],"multiple":[49,97],"versions":[50],"of":[51,60,71,213],"computer-aided":[53],"design":[54,182,204,234],"(CAD)":[55],"tools,":[56],"a":[58,82,101,121,160,228],"lack":[59],"modularity,":[61],"collaboration,":[62],"accessibility":[64],"beginners.":[66],"Moreover,":[67],"high":[69],"cost":[70,115],"large-scale":[72],"FPGAs":[73],"restricts":[74],"their":[75],"broader":[76],"adoption.":[77],"This":[78,175],"article":[79],"presents":[80],"CliCFPGA,":[81],"scalable":[83],"design,":[85],"verification,":[86,236],"prototyping":[88],"platform":[89,143],"designed":[90],"to":[91,129,200],"address":[92],"these":[93],"challenges.":[94],"By":[95],"integrating":[96],"CAD":[98],"tools":[99],"into":[100],"unified":[102],"environment":[103],"enabling":[105],"remote":[106],"compilation":[107],"on":[108],"shared":[109],"high-performance":[110],"servers,":[111],"CliCFPGA":[112,158,226],"reduces":[113],"setup":[117],"complexity.":[118],"It":[119],"offers":[120],"collaborative":[122,218],"workspace":[123,219],"with":[124,150,208],"debugging,":[126],"full":[127],"access":[128],"board":[131],"peripherals,":[132],"simultaneous":[134],"multiuser":[135],"testing.":[136],"To":[137],"accelerate":[138],"learning":[139],"development,":[141],"includes":[144],"an":[145,209],"intellectual":[146],"property":[147],"(IP)":[148],"library":[149],"preverified":[151],"accelerator":[153],"IP":[154],"cores.":[155],"In":[156],"addition,":[157],"features":[159],"large":[161],"language":[162,172],"model":[163],"(LLM)-assisted":[164],"tool":[165,176],"generating":[167],"verifying":[169],"description":[171],"(HDL)":[173],"code.":[174],"automates":[177],"error-prone":[178],"tasks,":[179],"significantly":[180],"reducing":[181],"time.":[183],"A":[184],"comprehensive":[185],"evaluation":[186],"combining":[187],"survey-based":[188],"feedback":[189],"metrics":[192],"confirms":[193],"platform\u2019s":[195],"impact.":[196],"Users":[197],"reported":[198],"up":[199],"three":[201],"times":[202],"verification":[206],"cycles,":[207],"average":[210],"satisfaction":[211],"rate":[212],"over":[214],"90%":[215],"LLM-assisted":[221],"features.":[222],"These":[223],"results":[224],"demonstrate":[225],"as":[227],"robust":[229],"solution":[230],"enhancing":[232],"supporting":[237],"diverse":[238],"applications":[239],"in":[240],"education,":[241],"research,":[242],"industry":[244],"while":[245],"promoting":[246],"cost-effective":[247],"sustainable":[249],"technological":[250],"development.":[251]},"counts_by_year":[],"updated_date":"2026-02-24T06:16:03.338239","created_date":"2025-12-29T00:00:00"}
