{"id":"https://openalex.org/W7126261290","doi":"https://doi.org/10.1109/tcsii.2026.3659753","title":"ScaDA-Rou: A Scalable, Deadlock-Free, and Adaptive Routing for 3-D Multi-Chiplet System","display_name":"ScaDA-Rou: A Scalable, Deadlock-Free, and Adaptive Routing for 3-D Multi-Chiplet System","publication_year":2026,"publication_date":"2026-01-30","ids":{"openalex":"https://openalex.org/W7126261290","doi":"https://doi.org/10.1109/tcsii.2026.3659753"},"language":null,"primary_location":{"id":"doi:10.1109/tcsii.2026.3659753","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2026.3659753","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113845189","display_name":"Lijing Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lijing Zhu","raw_affiliation_strings":["State Key Laboratory of Integrated Service Networks, Xidian University, Xian, China"],"raw_orcid":"https://orcid.org/0009-0000-4861-873X","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Service Networks, Xidian University, Xian, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049448415","display_name":"Huaxi Gu","orcid":"https://orcid.org/0000-0002-6409-2229"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huaxi Gu","raw_affiliation_strings":["State Key Laboratory of Integrated Service Networks, Xidian University, Xian, China"],"raw_orcid":"https://orcid.org/0000-0002-6409-2229","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Service Networks, Xidian University, Xian, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5124436470","display_name":"Yun Tan","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yun Tan","raw_affiliation_strings":["State Key Laboratory of Integrated Service Networks, Xidian University, Xian, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Service Networks, Xidian University, Xian, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"last","author":{"id":null,"display_name":"Guangming Zhang","orcid":"https://orcid.org/0009-0003-8204-6650"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guangming Zhang","raw_affiliation_strings":["State Key Laboratory of Integrated Service Networks, Xidian University, Xian, China"],"raw_orcid":"https://orcid.org/0009-0003-8204-6650","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Service Networks, Xidian University, Xian, China","institution_ids":["https://openalex.org/I149594827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I149594827"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.09818682,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"73","issue":"4","first_page":"433","last_page":"437"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9819999933242798,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9819999933242798,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.008799999952316284,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.002400000113993883,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.5954999923706055},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5037000179290771},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.47189998626708984},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4442000091075897},{"id":"https://openalex.org/keywords/routing-algorithm","display_name":"Routing algorithm","score":0.37709999084472656},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.3718999922275543},{"id":"https://openalex.org/keywords/static-routing","display_name":"Static routing","score":0.3294999897480011}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7473000288009644},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.5960999727249146},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.5954999923706055},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5037000179290771},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.47189998626708984},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4442000091075897},{"id":"https://openalex.org/C2984173633","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Routing algorithm","level":4,"score":0.37709999084472656},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.3718999922275543},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3319000005722046},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.3294999897480011},{"id":"https://openalex.org/C184896649","wikidata":"https://www.wikidata.org/wiki/Q290066","display_name":"Routing table","level":4,"score":0.3100999891757965},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.3070000112056732},{"id":"https://openalex.org/C24856439","wikidata":"https://www.wikidata.org/wiki/Q352483","display_name":"Adaptive routing","level":5,"score":0.30250000953674316},{"id":"https://openalex.org/C2777076873","wikidata":"https://www.wikidata.org/wiki/Q2291875","display_name":"Virtual channel","level":3,"score":0.2802000045776367},{"id":"https://openalex.org/C25344961","wikidata":"https://www.wikidata.org/wiki/Q192726","display_name":"Virtual machine","level":2,"score":0.27399998903274536},{"id":"https://openalex.org/C113429609","wikidata":"https://www.wikidata.org/wiki/Q4060699","display_name":"Deadlock prevention algorithms","level":3,"score":0.2736000120639801},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.25780001282691956}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2026.3659753","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2026.3659753","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2327951242","display_name":null,"funder_award_id":"JB210110","funder_id":"https://openalex.org/F4320335787","funder_display_name":"Fundamental Research Funds for the Central Universities"},{"id":"https://openalex.org/G2768299465","display_name":null,"funder_award_id":"QTZX24088","funder_id":"https://openalex.org/F4320335787","funder_display_name":"Fundamental Research Funds for the Central Universities"},{"id":"https://openalex.org/G3864541346","display_name":null,"funder_award_id":"2025YFB3003200","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"},{"id":"https://openalex.org/G6079809929","display_name":null,"funder_award_id":"2025RS-CXTD-004","funder_id":"https://openalex.org/F4320335802","funder_display_name":"Shaanxi Key Science and Technology Innovation Team Project"}],"funders":[{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null},{"id":"https://openalex.org/F4320335787","display_name":"Fundamental Research Funds for the Central Universities","ror":null},{"id":"https://openalex.org/F4320335802","display_name":"Shaanxi Key Science and Technology Innovation Team Project","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"With":[0],"the":[1,10,90,114,126,131,137],"rapid":[2],"advancement":[3],"of":[4,136,151],"high-performance":[5],"computing":[6],"and":[7,65,78,133,159],"AI":[8],"applications,":[9],"demand":[11],"for":[12,84,130],"computational":[13,30,47],"power":[14],"has":[15,20,35],"escalated":[16],"dramatically.":[17],"Chiplet":[18],"technology":[19,34],"emerged":[21],"as":[22],"a":[23,54,75],"pivotal":[24],"solution":[25],"to":[26,41,97],"meet":[27],"increasingly":[28],"complex":[29],"requirements.":[31],"Three-dimension":[32],"integration":[33],"further":[36],"enabled":[37],"three-dimensional":[38],"chiplet":[39,86],"systems":[40],"achieve":[42],"high-density":[43],"computing,":[44],"offering":[45],"substantial":[46],"capabilities.":[48],"However,":[49],"combining":[50],"several":[51,164],"chiplets":[52],"into":[53],"single":[55],"system-on-chip":[56],"(SoC)":[57],"presents":[58,73],"serious":[59],"deadlock":[60],"concerns":[61],"between":[62],"processor":[63],"units":[64],"chiplets.":[66],"To":[67],"address":[68],"this":[69,71],"challenge,":[70],"paper":[72],"ScaDA-Rou,":[74],"scalable,":[76],"deadlock-free,":[77],"adaptive":[79],"routing":[80,176],"algorithm":[81],"specifically":[82],"designed":[83],"3D":[85],"systems.":[87],"ScaDA-Rou":[88,145,169],"combines":[89],"turn":[91,111],"model":[92],"with":[93,163,174],"virtual":[94,127],"network":[95,103],"partitioning":[96],"efficiently":[98],"avoid":[99],"deadlocks":[100,106,118],"while":[101],"optimizing":[102],"performance.":[104],"In-plane":[105],"are":[107,122],"avoided":[108,123],"by":[109,124],"setting":[110],"restrictions":[112],"in":[113,153],"routers.":[115],"In":[116],"addition,":[117],"among":[119],"different":[120],"planes":[121,135],"separating":[125],"channels":[128],"used":[129],"source":[132],"destination":[134],"cross-plane":[138],"packets.":[139],"The":[140],"benchmark":[141],"results":[142],"demonstrate":[143],"that":[144],"achieves,":[146],"on":[147],"average,":[148],"performance":[149,172],"improvement":[150],"89.2%":[152],"latency":[154],"under":[155],"various":[156],"synthetic":[157],"traffic":[158],"system":[160],"sizes.":[161],"Moreover,":[162],"real":[165],"application":[166],"trace":[167],"scenarios,":[168],"achieves":[170],"higher":[171],"compared":[173],"traditional":[175],"algorithms.":[177]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2026-02-01T00:00:00"}
