{"id":"https://openalex.org/W4415482063","doi":"https://doi.org/10.1109/tcsii.2025.3624565","title":"A 1\u20138 b Reconfigurable 64 Mb STT-MRAM Near-Memory Computing Macro for Energy-Efficient AI-Edge Devices","display_name":"A 1\u20138 b Reconfigurable 64 Mb STT-MRAM Near-Memory Computing Macro for Energy-Efficient AI-Edge Devices","publication_year":2025,"publication_date":"2025-10-23","ids":{"openalex":"https://openalex.org/W4415482063","doi":"https://doi.org/10.1109/tcsii.2025.3624565"},"language":null,"primary_location":{"id":"doi:10.1109/tcsii.2025.3624565","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2025.3624565","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100606718","display_name":"Junyan Zhang","orcid":"https://orcid.org/0009-0006-1556-3975"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Junyan Zhang","raw_affiliation_strings":["School of Integrated Circuit, Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":"https://orcid.org/0009-0006-1556-3975","affiliations":[{"raw_affiliation_string":"School of Integrated Circuit, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100932603","display_name":"Jinyu Xiao","orcid":null},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinyu Xiao","raw_affiliation_strings":["School of Integrated Circuit, Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":"https://orcid.org/0009-0006-5556-4585","affiliations":[{"raw_affiliation_string":"School of Integrated Circuit, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007451729","display_name":"Jiahao Lu","orcid":"https://orcid.org/0000-0002-5793-4010"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiahao Lu","raw_affiliation_strings":["School of Integrated Circuit, Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":"https://orcid.org/0000-0002-5793-4010","affiliations":[{"raw_affiliation_string":"School of Integrated Circuit, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100440896","display_name":"Dongsheng Liu","orcid":"https://orcid.org/0000-0001-5571-1932"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dongsheng Liu","raw_affiliation_strings":["School of Integrated Circuit, Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":"https://orcid.org/0000-0001-5571-1932","affiliations":[{"raw_affiliation_string":"School of Integrated Circuit, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102941595","display_name":"Wenbiao Zhang","orcid":"https://orcid.org/0009-0008-9851-6414"},"institutions":[{"id":"https://openalex.org/I4210105979","display_name":"Signal Processing Devices (Sweden)","ror":"https://ror.org/01fs6c127","country_code":"SE","type":"company","lineage":["https://openalex.org/I4210105979"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Wenbiao Zhang","raw_affiliation_strings":["State Key Laboratory of Spintronic Devices and Technologies, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Spintronic Devices and Technologies, Hangzhou, China","institution_ids":["https://openalex.org/I4210105979"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058640875","display_name":"Xiang Feng","orcid":"https://orcid.org/0000-0003-1308-7849"},"institutions":[{"id":"https://openalex.org/I4210105979","display_name":"Signal Processing Devices (Sweden)","ror":"https://ror.org/01fs6c127","country_code":"SE","type":"company","lineage":["https://openalex.org/I4210105979"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Xiang Feng","raw_affiliation_strings":["State Key Laboratory of Spintronic Devices and Technologies, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Spintronic Devices and Technologies, Hangzhou, China","institution_ids":["https://openalex.org/I4210105979"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103178606","display_name":"Jianming Lei","orcid":"https://orcid.org/0000-0001-9123-9129"},"institutions":[{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianming Lei","raw_affiliation_strings":["School of Integrated Circuit, Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Integrated Circuit, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I47720641"]}]},{"author_position":"last","author":{"id":null,"display_name":"Dan Feng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210138186","display_name":"Wuhan National Laboratory for Optoelectronics","ror":"https://ror.org/03c9ncn37","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210138186"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dan Feng","raw_affiliation_strings":["School of Computer Science and Technology, Wuhan National Laboratory for Optoelectronics and the Key Laboratory of Information Storage System, Engineering Research Center for Data Storage Systems and Technology, Ministry of Education of China, Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Technology, Wuhan National Laboratory for Optoelectronics and the Key Laboratory of Information Storage System, Engineering Research Center for Data Storage Systems and Technology, Ministry of Education of China, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I4210138186"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.315,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.56812964,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"72","issue":"12","first_page":"2017","last_page":"2021"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.8252999782562256},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5533000230789185},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5400000214576721},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.5016000270843506},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.4431999921798706},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.43959999084472656},{"id":"https://openalex.org/keywords/random-access","display_name":"Random access","score":0.429500013589859},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.40799999237060547},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4025000035762787}],"concepts":[{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.8252999782562256},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7081000208854675},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5533000230789185},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5400000214576721},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.5016000270843506},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.4431999921798706},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.43959999084472656},{"id":"https://openalex.org/C101722063","wikidata":"https://www.wikidata.org/wiki/Q218825","display_name":"Random access","level":2,"score":0.429500013589859},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.40799999237060547},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4025000035762787},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37540000677108765},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3734000027179718},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.36090001463890076},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.35190001130104065},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.3292999863624573},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.31869998574256897},{"id":"https://openalex.org/C60448319","wikidata":"https://www.wikidata.org/wiki/Q154021","display_name":"Block cipher mode of operation","level":2,"score":0.3093000054359436},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.3050999939441681},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.3012000024318695},{"id":"https://openalex.org/C138827492","wikidata":"https://www.wikidata.org/wiki/Q6661985","display_name":"Data processing","level":2,"score":0.295199990272522},{"id":"https://openalex.org/C144171764","wikidata":"https://www.wikidata.org/wiki/Q48103","display_name":"Torque","level":2,"score":0.27129998803138733},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.26440000534057617},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.2623000144958496},{"id":"https://openalex.org/C2778456923","wikidata":"https://www.wikidata.org/wiki/Q5337692","display_name":"Edge computing","level":3,"score":0.26170000433921814},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.25679999589920044},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.2567000091075897},{"id":"https://openalex.org/C89198739","wikidata":"https://www.wikidata.org/wiki/Q3079880","display_name":"Data stream mining","level":2,"score":0.251800000667572},{"id":"https://openalex.org/C123593499","wikidata":"https://www.wikidata.org/wiki/Q6008583","display_name":"In-Memory Processing","level":5,"score":0.2517000138759613},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.25130000710487366},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.2502000033855438}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2025.3624565","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2025.3624565","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3688453874","display_name":null,"funder_award_id":"2024YFB4505400","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"},{"id":"https://openalex.org/G7118155122","display_name":null,"funder_award_id":"62134002","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G832233188","display_name":null,"funder_award_id":"2024YFB4505400","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W2591601611","https://openalex.org/W3135461891","https://openalex.org/W3135906938","https://openalex.org/W3139521791","https://openalex.org/W3208067593","https://openalex.org/W4220673325","https://openalex.org/W4221038786","https://openalex.org/W4221039638","https://openalex.org/W4225364593","https://openalex.org/W4247198796","https://openalex.org/W4286571697","https://openalex.org/W4313839325","https://openalex.org/W4360606474","https://openalex.org/W4360607286","https://openalex.org/W4376456681","https://openalex.org/W4376607860","https://openalex.org/W4385217898","https://openalex.org/W4387917719","https://openalex.org/W4392188061"],"related_works":[],"abstract_inverted_index":{"This":[0],"brief":[1],"presents":[2,107],"an":[3],"nonvolatile":[4],"near-memory-compute":[5],"(nvNMC)":[6],"macro":[7,16,84],"for":[8],"edge":[9],"artificial":[10],"intelligence":[11],"(AI)":[12],"de-vices.":[13],"The":[14,36,56,82],"proposed":[15,83],"is":[17],"interconnected":[18],"in":[19,95],"groups":[20],"of":[21,112,117],"4":[22],"sub-macros":[23],"per":[24],"line,":[25],"enabling":[26],"sub-macro":[27,37],"level":[28],"task":[29],"scheduling":[30],"through":[31],"a":[32,70,86,96,109],"customized":[33],"micro-instruction":[34],"set.":[35],"ar-chitecture":[38],"employs":[39],"dual-clock":[40],"domains":[41],"and":[42,53,68,77,114],"hierarchical":[43],"pipelin-ing":[44],"to":[45,74],"enhance":[46],"the":[47],"overall":[48],"chip\u2019s":[49],"data":[50,71],"throughput,":[51],"computility,":[52],"energy":[54,115],"efficiency.":[55],"multiply-and-accumulate":[57],"(MAC)":[58],"unit":[59],"achieves":[60],"1-8b":[61],"reconfigurable":[62],"input/weight":[63],"precision":[64],"via":[65],"bit-serial":[66],"computing":[67],"incorporates":[69],"bypass":[72],"path":[73],"boost":[75],"perfor-mance":[76],"efficiency":[78,116],"during":[79],"1b":[80,121],"computations.":[81],"integrates":[85],"64Mb":[87],"spin-transfer":[88],"torque":[89],"magnetic":[90],"random":[91],"access":[92],"memory":[93],"(STT-MRAM)":[94],"51.29mm<sup":[97],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[98],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[99],"die":[100],"area":[101],"using":[102],"28nm":[103],"CMOS":[104],"technology.":[105],"It":[106],"that":[108],"peak":[110],"computility":[111],"30.81TOPS":[113],"316":[118],"TOPS/W":[119],"at":[120],"precision.":[122]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-25T09:21:30.201066","created_date":"2025-10-23T00:00:00"}
