{"id":"https://openalex.org/W7092692354","doi":"https://doi.org/10.1109/tcsii.2025.3623997","title":"MorphBungee-Tiny: An Ultra-Low-Cost FPGA Implementation of Neuromorphic Architecture With High-Accuracy On-Chip E-Prop Learning","display_name":"MorphBungee-Tiny: An Ultra-Low-Cost FPGA Implementation of Neuromorphic Architecture With High-Accuracy On-Chip E-Prop Learning","publication_year":2025,"publication_date":"2025-10-20","ids":{"openalex":"https://openalex.org/W7092692354","doi":"https://doi.org/10.1109/tcsii.2025.3623997"},"language":null,"primary_location":{"id":"doi:10.1109/tcsii.2025.3623997","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2025.3623997","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Zhengqing Zhong","orcid":"https://orcid.org/0009-0006-2883-4287"},"institutions":[{"id":"https://openalex.org/I158842170","display_name":"Chongqing University","ror":"https://ror.org/023rhb549","country_code":"CN","type":"education","lineage":["https://openalex.org/I158842170"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhengqing Zhong","raw_affiliation_strings":["School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China","institution_ids":["https://openalex.org/I158842170"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jialin Yang","orcid":"https://orcid.org/0009-0003-3714-3689"},"institutions":[{"id":"https://openalex.org/I158842170","display_name":"Chongqing University","ror":"https://ror.org/023rhb549","country_code":"CN","type":"education","lineage":["https://openalex.org/I158842170"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jialin Yang","raw_affiliation_strings":["School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China","institution_ids":["https://openalex.org/I158842170"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Haibing Wang","orcid":"https://orcid.org/0009-0000-3663-9138"},"institutions":[{"id":"https://openalex.org/I158842170","display_name":"Chongqing University","ror":"https://ror.org/023rhb549","country_code":"CN","type":"education","lineage":["https://openalex.org/I158842170"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haibing Wang","raw_affiliation_strings":["School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China","institution_ids":["https://openalex.org/I158842170"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Ying Jiang","orcid":"https://orcid.org/0009-0002-0642-4106"},"institutions":[{"id":"https://openalex.org/I158842170","display_name":"Chongqing University","ror":"https://ror.org/023rhb549","country_code":"CN","type":"education","lineage":["https://openalex.org/I158842170"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ying Jiang","raw_affiliation_strings":["School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China","institution_ids":["https://openalex.org/I158842170"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Yingcheng Lin","orcid":"https://orcid.org/0000-0002-7478-3103"},"institutions":[{"id":"https://openalex.org/I158842170","display_name":"Chongqing University","ror":"https://ror.org/023rhb549","country_code":"CN","type":"education","lineage":["https://openalex.org/I158842170"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yingcheng Lin","raw_affiliation_strings":["School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China","institution_ids":["https://openalex.org/I158842170"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Ping Gan","orcid":null},"institutions":[{"id":"https://openalex.org/I158842170","display_name":"Chongqing University","ror":"https://ror.org/023rhb549","country_code":"CN","type":"education","lineage":["https://openalex.org/I158842170"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ping Gan","raw_affiliation_strings":["School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China","institution_ids":["https://openalex.org/I158842170"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Liyuan Liu","orcid":"https://orcid.org/0000-0003-2585-323X"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liyuan Liu","raw_affiliation_strings":["Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210149211","https://openalex.org/I19820366"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Liang Liang","orcid":"https://orcid.org/0000-0002-2778-455X"},"institutions":[{"id":"https://openalex.org/I158842170","display_name":"Chongqing University","ror":"https://ror.org/023rhb549","country_code":"CN","type":"education","lineage":["https://openalex.org/I158842170"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liang Liang","raw_affiliation_strings":["School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China","institution_ids":["https://openalex.org/I158842170"]}]},{"author_position":"last","author":{"id":null,"display_name":"Cong Shi","orcid":"https://orcid.org/0000-0003-0040-4411"},"institutions":[{"id":"https://openalex.org/I158842170","display_name":"Chongqing University","ror":"https://ror.org/023rhb549","country_code":"CN","type":"education","lineage":["https://openalex.org/I158842170"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Cong Shi","raw_affiliation_strings":["School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics and Communication Engineering, Chongqing University, Chongqing, China","institution_ids":["https://openalex.org/I158842170"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I158842170"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.5102887,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"72","issue":"12","first_page":"2012","last_page":"2016"},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9509000182151794,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9509000182151794,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12611","display_name":"Neural Networks and Reservoir Computing","score":0.01209999993443489,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.011300000362098217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.675000011920929},{"id":"https://openalex.org/keywords/neuromorphic-engineering","display_name":"Neuromorphic engineering","score":0.6155999898910522},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5157999992370605},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.5116000175476074},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.4878999888896942},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4878000020980835},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.42289999127388},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4147000014781952},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.39579999446868896}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7613000273704529},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.675000011920929},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6665999889373779},{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.6155999898910522},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5157999992370605},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.5116000175476074},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.4878999888896942},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4878000020980835},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4404999911785126},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.42289999127388},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4147000014781952},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.39579999446868896},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.34599998593330383},{"id":"https://openalex.org/C175309249","wikidata":"https://www.wikidata.org/wiki/Q725864","display_name":"Pipeline transport","level":2,"score":0.3398999869823456},{"id":"https://openalex.org/C108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","level":2,"score":0.335999995470047},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.3353999853134155},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3127000033855438},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3109999895095825},{"id":"https://openalex.org/C46637626","wikidata":"https://www.wikidata.org/wiki/Q6693015","display_name":"Low latency (capital markets)","level":2,"score":0.3028999865055084},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.2985999882221222},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.29840001463890076},{"id":"https://openalex.org/C161824985","wikidata":"https://www.wikidata.org/wiki/Q919509","display_name":"Vector processor","level":2,"score":0.28690001368522644},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2833999991416931},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.2833999991416931},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2809000015258789},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.2732999920845032},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.27300000190734863},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.26460000872612},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.26190000772476196},{"id":"https://openalex.org/C509933004","wikidata":"https://www.wikidata.org/wiki/Q194163","display_name":"Broadband","level":2,"score":0.26030001044273376},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.25769999623298645},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.25690001249313354},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.25440001487731934}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2025.3623997","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2025.3623997","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7239735722541809,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1695065985","https://openalex.org/W2138913040","https://openalex.org/W2783525259","https://openalex.org/W2795655975","https://openalex.org/W2966081953","https://openalex.org/W3012075737","https://openalex.org/W3043133474","https://openalex.org/W3134388707","https://openalex.org/W3202272897","https://openalex.org/W4206199833","https://openalex.org/W4284973893","https://openalex.org/W4308259483","https://openalex.org/W4309263211","https://openalex.org/W4317796237","https://openalex.org/W4376652608","https://openalex.org/W4388430470","https://openalex.org/W4388692307","https://openalex.org/W4390777363","https://openalex.org/W4391341605","https://openalex.org/W4392928956","https://openalex.org/W4394595737","https://openalex.org/W4396505671","https://openalex.org/W4399513280","https://openalex.org/W4401109788","https://openalex.org/W4401537204","https://openalex.org/W4401596736","https://openalex.org/W4403917454","https://openalex.org/W4406387820","https://openalex.org/W4406694068","https://openalex.org/W4406894708","https://openalex.org/W4406948865"],"related_works":[],"abstract_inverted_index":{"Neuromorphic":[0],"processors":[1],"leverage":[2],"brain-inspired":[3],"spike-based":[4],"sparse":[5],"computation":[6],"to":[7,74],"gain":[8],"energy":[9,132],"efficiency":[10],"for":[11,19,53],"edge-node":[12],"intelligence.":[13],"Yet,":[14],"achieving":[15],"high-accuracy":[16],"on-chip":[17,56,124],"learning":[18,125],"in-situ":[20],"self-adaptation":[21],"at":[22],"a":[23,27,31,61,76,105],"low":[24,28],"cost":[25,130],"and":[26,70,111,131],"latency":[29],"poses":[30],"key":[32],"challenge.":[33],"To":[34],"address":[35],"this,":[36],"we":[37],"present":[38],"the":[39,71,85,91,94],"4th":[40],"generation":[41],"of":[42,68,123],"our":[43,49,102],"MorphBungee":[44],"processors.":[45],"The":[46],"processor":[47],"adopts":[48],"integer":[50],"e-prop":[51],"algorithm":[52],"high-accuracy,":[54],"low-cost":[55],"SNN":[57],"training.":[58],"It":[59],"employs":[60],"vector-scalar":[62],"dual-core":[63],"architecture":[64],"with":[65],"2":[66],"levels":[67],"pipelines":[69],"spike/error-event-driven":[72],"paradigm":[73],"ensure":[75],"high":[77],"sample":[78],"throughput.":[79],"A":[80],"logically":[81],"transposable":[82],"memory":[83],"enables":[84],"vector":[86],"core\u2019s":[87],"flexible":[88],"parallelism":[89],"along":[90],"neuron-":[92],"or":[93],"synapse-dimension":[95],"in":[96,121],"different":[97],"processing":[98,127],"phases.":[99],"We":[100],"prototyped":[101],"design":[103],"on":[104],"very-low-cost":[106],"Xilinx":[107],"Zynq-7010":[108],"FPGA":[109],"chip,":[110],"demonstrated":[112],"its":[113],"overall":[114],"performance":[115],"superiority":[116],"over":[117],"other":[118],"related":[119],"works,":[120],"terms":[122],"accuracy,":[126],"speed,":[128],"resource":[129],"efficiency.":[133]},"counts_by_year":[],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-21T00:00:00"}
