{"id":"https://openalex.org/W4414908351","doi":"https://doi.org/10.1109/tcsii.2025.3618605","title":"Closed-Loop Pole Analysis via Output Impedance in Miller-Compensated Amplifiers","display_name":"Closed-Loop Pole Analysis via Output Impedance in Miller-Compensated Amplifiers","publication_year":2025,"publication_date":"2025-10-07","ids":{"openalex":"https://openalex.org/W4414908351","doi":"https://doi.org/10.1109/tcsii.2025.3618605"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2025.3618605","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2025.3618605","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090014319","display_name":"Haochang Zhi","orcid":"https://orcid.org/0009-0001-1198-6915"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Haochang Zhi","raw_affiliation_strings":["National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China","School of Integrated Circuits, National ASIC Center, Southeast University, Nanjing, China"],"raw_orcid":"https://orcid.org/0009-0001-1198-6915","affiliations":[{"raw_affiliation_string":"National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]},{"raw_affiliation_string":"School of Integrated Circuits, National ASIC Center, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088178933","display_name":"Shaojie Xu","orcid":"https://orcid.org/0000-0003-0283-2436"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shaojie Xu","raw_affiliation_strings":["National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China","School of Integrated Circuits, National ASIC Center, Southeast University, Nanjing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]},{"raw_affiliation_string":"School of Integrated Circuits, National ASIC Center, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100334715","display_name":"Jintao Li","orcid":"https://orcid.org/0000-0003-0403-6767"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]},{"id":"https://openalex.org/I4210145761","display_name":"Shenzhen Institutes of Advanced Technology","ror":"https://ror.org/04gh4er46","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210145761"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jintao Li","raw_affiliation_strings":["Shenzhen Institute for Advanced Study, University of Electronic Science and Technology of China (UESTC), Shenzhen, China","Shenzhen Institute for Advanced Study, UESTC, Shenzhen, China"],"raw_orcid":"https://orcid.org/0000-0003-0403-6767","affiliations":[{"raw_affiliation_string":"Shenzhen Institute for Advanced Study, University of Electronic Science and Technology of China (UESTC), Shenzhen, China","institution_ids":["https://openalex.org/I150229711"]},{"raw_affiliation_string":"Shenzhen Institute for Advanced Study, UESTC, Shenzhen, China","institution_ids":["https://openalex.org/I4210145761"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Tong Zhou","orcid":"https://orcid.org/0009-0006-6532-4606"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tong Zhou","raw_affiliation_strings":["School of Integrated Circuits, Zhejiang University, Hangzhou, China"],"raw_orcid":"https://orcid.org/0009-0006-6532-4606","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100743577","display_name":"Yun Li","orcid":"https://orcid.org/0000-0002-6575-1839"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]},{"id":"https://openalex.org/I4210145761","display_name":"Shenzhen Institutes of Advanced Technology","ror":"https://ror.org/04gh4er46","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210145761"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yun Li","raw_affiliation_strings":["Shenzhen Institute for Advanced Study, University of Electronic Science and Technology of China (UESTC), Shenzhen, China","Shenzhen Institute for Advanced Study, UESTC, Shenzhen, China"],"raw_orcid":"https://orcid.org/0000-0002-6575-1839","affiliations":[{"raw_affiliation_string":"Shenzhen Institute for Advanced Study, University of Electronic Science and Technology of China (UESTC), Shenzhen, China","institution_ids":["https://openalex.org/I150229711"]},{"raw_affiliation_string":"Shenzhen Institute for Advanced Study, UESTC, Shenzhen, China","institution_ids":["https://openalex.org/I4210145761"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057291086","display_name":"Weiwei Shan","orcid":"https://orcid.org/0000-0001-5520-1326"},"institutions":[{"id":"https://openalex.org/I76569877","display_name":"Southeast University","ror":"https://ror.org/04ct4d772","country_code":"CN","type":"education","lineage":["https://openalex.org/I76569877"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weiwei Shan","raw_affiliation_strings":["National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China","School of Integrated Circuits, National ASIC Center, Southeast University, Nanjing, China"],"raw_orcid":"https://orcid.org/0000-0001-5520-1326","affiliations":[{"raw_affiliation_string":"National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]},{"raw_affiliation_string":"School of Integrated Circuits, National ASIC Center, Southeast University, Nanjing, China","institution_ids":["https://openalex.org/I76569877"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069121787","display_name":"Wanyuan Qu","orcid":"https://orcid.org/0000-0002-8318-9878"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wanyuan Qu","raw_affiliation_strings":["School of Integrated Circuits, Zhejiang University, Hangzhou, China"],"raw_orcid":"https://orcid.org/0000-0002-8318-9878","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5090014319"],"corresponding_institution_ids":["https://openalex.org/I76569877"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.2538336,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"72","issue":"11","first_page":"1715","last_page":"1719"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12564","display_name":"Sensor Technology and Measurement Systems","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.6251999735832214},{"id":"https://openalex.org/keywords/electrical-impedance","display_name":"Electrical impedance","score":0.5514000058174133},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.5367000102996826},{"id":"https://openalex.org/keywords/output-impedance","display_name":"Output impedance","score":0.4390000104904175},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.4334999918937683},{"id":"https://openalex.org/keywords/pole\u2013zero-plot","display_name":"Pole\u2013zero plot","score":0.40610000491142273},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.3995000123977661},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3995000123977661},{"id":"https://openalex.org/keywords/compensation","display_name":"Compensation (psychology)","score":0.3910999894142151},{"id":"https://openalex.org/keywords/point","display_name":"Point (geometry)","score":0.3779999911785126}],"concepts":[{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.6251999735832214},{"id":"https://openalex.org/C17829176","wikidata":"https://www.wikidata.org/wiki/Q179043","display_name":"Electrical impedance","level":2,"score":0.5514000058174133},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.5367000102996826},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4819999933242798},{"id":"https://openalex.org/C58112919","wikidata":"https://www.wikidata.org/wiki/Q631203","display_name":"Output impedance","level":3,"score":0.4390000104904175},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.4334999918937683},{"id":"https://openalex.org/C43656286","wikidata":"https://www.wikidata.org/wiki/Q2100961","display_name":"Pole\u2013zero plot","level":3,"score":0.40610000491142273},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.3995000123977661},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3995000123977661},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.39739999175071716},{"id":"https://openalex.org/C2780023022","wikidata":"https://www.wikidata.org/wiki/Q1338171","display_name":"Compensation (psychology)","level":2,"score":0.3910999894142151},{"id":"https://openalex.org/C28719098","wikidata":"https://www.wikidata.org/wiki/Q44946","display_name":"Point (geometry)","level":2,"score":0.3779999911785126},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.37709999084472656},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.36160001158714294},{"id":"https://openalex.org/C89880566","wikidata":"https://www.wikidata.org/wiki/Q323477","display_name":"RLC circuit","level":4,"score":0.361299991607666},{"id":"https://openalex.org/C26262908","wikidata":"https://www.wikidata.org/wiki/Q1307489","display_name":"Input impedance","level":3,"score":0.34769999980926514},{"id":"https://openalex.org/C8590192","wikidata":"https://www.wikidata.org/wiki/Q1054694","display_name":"Frequency response","level":2,"score":0.34599998593330383},{"id":"https://openalex.org/C131782439","wikidata":"https://www.wikidata.org/wiki/Q1455581","display_name":"Frequency compensation","level":4,"score":0.3456999957561493},{"id":"https://openalex.org/C32946077","wikidata":"https://www.wikidata.org/wiki/Q618079","display_name":"Network analysis","level":2,"score":0.3431999981403351},{"id":"https://openalex.org/C81455027","wikidata":"https://www.wikidata.org/wiki/Q7180955","display_name":"Phase margin","level":5,"score":0.3409999907016754},{"id":"https://openalex.org/C22762622","wikidata":"https://www.wikidata.org/wiki/Q628904","display_name":"Operating point","level":2,"score":0.3343999981880188},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.3269999921321869},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3167000114917755},{"id":"https://openalex.org/C81299745","wikidata":"https://www.wikidata.org/wiki/Q334269","display_name":"Transfer function","level":2,"score":0.29820001125335693},{"id":"https://openalex.org/C89123640","wikidata":"https://www.wikidata.org/wiki/Q1523756","display_name":"Instrumentation amplifier","level":5,"score":0.29589998722076416},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.29330000281333923},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.289900004863739},{"id":"https://openalex.org/C139210041","wikidata":"https://www.wikidata.org/wiki/Q2145840","display_name":"Resonance (particle physics)","level":2,"score":0.27889999747276306},{"id":"https://openalex.org/C199943209","wikidata":"https://www.wikidata.org/wiki/Q1271153","display_name":"Loop gain","level":3,"score":0.27309998869895935},{"id":"https://openalex.org/C186886427","wikidata":"https://www.wikidata.org/wiki/Q5441213","display_name":"Feedback loop","level":2,"score":0.26750001311302185},{"id":"https://openalex.org/C11722477","wikidata":"https://www.wikidata.org/wiki/Q1056298","display_name":"Differential amplifier","level":4,"score":0.26100000739097595},{"id":"https://openalex.org/C612350","wikidata":"https://www.wikidata.org/wiki/Q1761108","display_name":"Impedance matching","level":3,"score":0.25459998846054077},{"id":"https://openalex.org/C68742264","wikidata":"https://www.wikidata.org/wiki/Q1736442","display_name":"Current-feedback operational amplifier","level":5,"score":0.2522999942302704},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2515999972820282}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2025.3618605","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2025.3618605","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G4075270565","display_name":null,"funder_award_id":"92473106","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G5227578763","display_name":null,"funder_award_id":"92464302","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G6422954184","display_name":null,"funder_award_id":"2022YFB4400600","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"},{"id":"https://openalex.org/G7332580563","display_name":null,"funder_award_id":"92464204","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1673818769","https://openalex.org/W1950735355","https://openalex.org/W2004391179","https://openalex.org/W2020763844","https://openalex.org/W2052728226","https://openalex.org/W2102029541","https://openalex.org/W2104728751","https://openalex.org/W2125776391","https://openalex.org/W2130044447","https://openalex.org/W2154237706","https://openalex.org/W2551453206","https://openalex.org/W2757448394","https://openalex.org/W3034452075","https://openalex.org/W4312540172","https://openalex.org/W4386869804","https://openalex.org/W4401567585","https://openalex.org/W4409683793"],"related_works":[],"abstract_inverted_index":{"A":[0],"closed-loop":[1,27],"pole":[2],"analysis":[3,15],"(CLPA)":[4],"method":[5],"is":[6,90],"presented":[7],"for":[8,146],"Miller-compensated":[9],"multistage":[10],"amplifiers.":[11],"CLPA":[12,55],"broadens":[13],"design-oriented":[14],"by":[16],"adopting":[17],"an":[18,113,138],"impedance-based":[19],"point":[20],"of":[21,117,128,142],"view,":[22],"directly":[23],"relating":[24],"T/(1+T)":[25],"to":[26,71],"response,":[28],"along":[29],"with":[30,121],"clear":[31],"circuit":[32],"design":[33,52],"specifications":[34],"(g<sub":[35],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[36,39,42,46,115,119,140,144],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">m2</sub>,":[37],"R<sub":[38],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">o2</sub>,":[40],"C<sub":[41],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">p2</sub>":[43],"and":[44,50,69,112,137,153],"g<sub":[45],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">m3</sub>),":[47],"offering":[48],"intuitive":[49],"quantitative":[51],"insights.":[53],"Specifically,":[54],"modeling":[56],"the":[57],"inner":[58],"Miller":[59],"loop":[60],"as":[61],"a":[62,81,99,108,122,129,147],"second-order":[63],"RLC":[64],"cell":[65],"allows":[66],"natural":[67],"frequency":[68],"damping":[70],"be":[72],"extracted":[73],"from":[74],"output":[75],"impedance":[76],"breakpoints.":[77],"Leveraging":[78],"this":[79],"connection,":[80],"resonance":[82],"control":[83],"scalable":[84],"single-Miller":[85],"capacitor":[86],"compensation":[87],"(RCSMC)":[88],"topology":[89],"developed.":[91],"Measurement":[92],"results":[93],"in":[94],"28nm":[95],"CMOS":[96],"show":[97],"that":[98],"three-stage":[100],"RCSMC":[101,131],"amplifier":[102,132],"achieves":[103],"124":[104],"dB":[105,135],"DC":[106],"gain,":[107],"1.16MHz":[109],"gain-bandwidth":[110],"product,":[111],"FOM<sub":[114,139],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">1</sub>":[116,141],"39,456MHz\u00b7pF/(\u03bcW\u00b7mm<sup":[118],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>)":[120,145],"200":[123],"pF":[124],"load,":[125,150],"while":[126],"simulations":[127],"four-stage":[130],"reach":[133],"120":[134],"gain":[136],"1,137,800MHz\u00b7pF/(\u03bcW\u00b7mm<sup":[143],"64":[148],"nF":[149],"demonstrating":[151],"performance":[152],"scalability.":[154]},"counts_by_year":[],"updated_date":"2025-11-07T23:20:04.922697","created_date":"2025-10-10T00:00:00"}