{"id":"https://openalex.org/W4400187671","doi":"https://doi.org/10.1109/tcsii.2024.3421323","title":"A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations","display_name":"A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations","publication_year":2024,"publication_date":"2024-07-01","ids":{"openalex":"https://openalex.org/W4400187671","doi":"https://doi.org/10.1109/tcsii.2024.3421323"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2024.3421323","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsii.2024.3421323","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1109/tcsii.2024.3421323","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011214102","display_name":"Fabio Frustaci","orcid":"https://orcid.org/0000-0001-5795-4321"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fabio Frustaci","raw_affiliation_strings":["Department of Informatics, Modeling, Electronics and Systems Engineering, University of Calabria, Rende, Italy"],"raw_orcid":"https://orcid.org/0000-0001-5795-4321","affiliations":[{"raw_affiliation_string":"Department of Informatics, Modeling, Electronics and Systems Engineering, University of Calabria, Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035230230","display_name":"Fanny Spagnolo","orcid":"https://orcid.org/0000-0002-2197-4563"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fanny Spagnolo","raw_affiliation_strings":["Department of Informatics, Modeling, Electronics and Systems Engineering, University of Calabria, Rende, Italy"],"raw_orcid":"https://orcid.org/0000-0002-2197-4563","affiliations":[{"raw_affiliation_string":"Department of Informatics, Modeling, Electronics and Systems Engineering, University of Calabria, Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003003043","display_name":"Pasquale Corsonello","orcid":"https://orcid.org/0000-0002-9528-1110"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Pasquale Corsonello","raw_affiliation_strings":["Department of Informatics, Modeling, Electronics and Systems Engineering, University of Calabria, Rende, Italy"],"raw_orcid":"https://orcid.org/0000-0002-9528-1110","affiliations":[{"raw_affiliation_string":"Department of Informatics, Modeling, Electronics and Systems Engineering, University of Calabria, Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074662921","display_name":"Stefania Perri","orcid":"https://orcid.org/0000-0003-1363-9201"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Stefania Perri","raw_affiliation_strings":["Department of Mechanical, Energy and Management Engineering, University of Calabria, Rende, Italy"],"raw_orcid":"https://orcid.org/0000-0003-1363-9201","affiliations":[{"raw_affiliation_string":"Department of Mechanical, Energy and Management Engineering, University of Calabria, Rende, Italy","institution_ids":["https://openalex.org/I45204951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I45204951"],"apc_list":null,"apc_paid":null,"fwci":6.7157,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.97999735,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":"71","issue":"12","first_page":"4964","last_page":"4968"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9847000241279602,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8193589448928833},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.7481358051300049},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.7081375122070312},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.627891480922699},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5823279619216919},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4356966018676758},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4114295244216919},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36957526206970215},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3291153907775879},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08768856525421143}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8193589448928833},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.7481358051300049},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.7081375122070312},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.627891480922699},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5823279619216919},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4356966018676758},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4114295244216919},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36957526206970215},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3291153907775879},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08768856525421143},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2024.3421323","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsii.2024.3421323","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/tcsii.2024.3421323","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsii.2024.3421323","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6600000262260437}],"awards":[],"funders":[{"id":"https://openalex.org/F4320310077","display_name":"National Research Centre","ror":"https://ror.org/02n85j827"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1717406790","https://openalex.org/W2014905809","https://openalex.org/W2033711887","https://openalex.org/W2117205818","https://openalex.org/W2135205174","https://openalex.org/W2524910869","https://openalex.org/W2947486590","https://openalex.org/W3036146501","https://openalex.org/W3091761257","https://openalex.org/W3097403316","https://openalex.org/W3107348029","https://openalex.org/W3140517496","https://openalex.org/W3196521403","https://openalex.org/W3201551371","https://openalex.org/W3207886650","https://openalex.org/W4226249155","https://openalex.org/W4309765387","https://openalex.org/W4312366852","https://openalex.org/W4312377982","https://openalex.org/W4319997236","https://openalex.org/W4385819628","https://openalex.org/W4386764161","https://openalex.org/W4387415270","https://openalex.org/W4391582695","https://openalex.org/W6784857538"],"related_works":["https://openalex.org/W2120447654","https://openalex.org/W2977179488","https://openalex.org/W1876592433","https://openalex.org/W2083269738","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2387078853","https://openalex.org/W2374455716","https://openalex.org/W2363990172"],"abstract_inverted_index":{"This":[0],"brief":[1],"presents":[2],"an":[3,28,104,128,150],"effective":[4],"way":[5],"to":[6,44,58,68,89,98,137,146,154],"design":[7,26],"high-throughput":[8],"and":[9,127,149,174],"low-power":[10],"True":[11],"Random":[12],"Number":[13],"Generators":[14],"(TRNGs)":[15],"for":[16,53],"Field":[17],"Programmable":[18],"Gate":[19],"Array":[20],"(FPGA)-based":[21],"digital":[22],"systems.":[23],"The":[24,157],"proposed":[25,85],"makes":[27],"unconventional":[29],"usage":[30],"of":[31,124,131,165],"the":[32,40,84,110,118,166,170,175],"Digital":[33],"Signal":[34],"Processing":[35],"(DSP)":[36],"slice":[37],"embedded":[38],"within":[39,72],"AMD-Xilinx":[41,111],"FPGA":[42],"devices":[43],"implement":[45],"high":[46],"jitter":[47],"ring":[48],"oscillators":[49,71],"as":[50],"entropy":[51],"sources":[52],"efficient":[54],"TRNG":[55,81,159],"designs.":[56],"Thanks":[57],"its":[59],"wide":[60],"bit-width":[61],"output,":[62],"several":[63],"configurations":[64],"can":[65],"be":[66],"enabled":[67],"group":[69],"multiple":[70],"a":[73,78,80,99,122,142],"single":[74],"DSP":[75],"slice.":[76],"As":[77],"result,":[79],"designed":[82],"through":[83],"scheme":[86],"outputs":[87],"up":[88,145,153],"4":[90],"random":[91],"bits":[92],"per":[93],"clock":[94],"cycle,":[95],"thus":[96],"leading":[97],"considerably":[100],"high-throughput,":[101],"while":[102],"exploiting":[103],"ultra-compact":[105],"architecture.":[106],"When":[107,135],"implemented":[108],"on":[109,115],"Zynq":[112],"XC7Z020":[113],"System":[114],"Chip":[116],"(SoC),":[117],"new":[119,158],"architecture":[120],"achieves":[121,141],"throughput":[123,143],"800W106":[125],"bit/sec":[126],"energy":[129,151],"consumption":[130,152],"only":[132],"22":[133],"pJ/bit.":[134],"compared":[136],"state-of-the-art":[138],"competitors":[139],"it":[140],"rate":[144],"2.6W":[147],"higher":[148],"8W":[155],"lower.":[156],"has":[160],"been":[161],"validated":[162],"by":[163],"means":[164],"NIST":[167,171],"SP":[168],"800-22,":[169],"800":[172],"90B":[173],"AIS":[176],"statistical":[177],"tests.":[178]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":15},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}