{"id":"https://openalex.org/W4389776295","doi":"https://doi.org/10.1109/tcsii.2023.3343470","title":"A TDC With Integrated Snapshot Circuit and Calibration in 28-nm CMOS","display_name":"A TDC With Integrated Snapshot Circuit and Calibration in 28-nm CMOS","publication_year":2023,"publication_date":"2023-12-15","ids":{"openalex":"https://openalex.org/W4389776295","doi":"https://doi.org/10.1109/tcsii.2023.3343470"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2023.3343470","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2023.3343470","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037074132","display_name":"Tim Lauber","orcid":"https://orcid.org/0009-0004-6821-3368"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Tim Lauber","raw_affiliation_strings":["Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"raw_orcid":"https://orcid.org/0009-0004-6821-3368","affiliations":[{"raw_affiliation_string":"Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021970559","display_name":"Lantao Wang","orcid":"https://orcid.org/0000-0001-6535-3278"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Lantao Wang","raw_affiliation_strings":["Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"raw_orcid":"https://orcid.org/0000-0001-6535-3278","affiliations":[{"raw_affiliation_string":"Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049594173","display_name":"Johannes Bastl","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Johannes Bastl","raw_affiliation_strings":["Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5092357717","display_name":"Kenny Vohl","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Kenny Vohl","raw_affiliation_strings":["Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033528054","display_name":"Ralf Wunderlich","orcid":"https://orcid.org/0000-0001-5841-6293"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ralf Wunderlich","raw_affiliation_strings":["Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039003474","display_name":"Stefan Heinen","orcid":"https://orcid.org/0009-0001-7568-8116"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Stefan Heinen","raw_affiliation_strings":["Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5037074132"],"corresponding_institution_ids":["https://openalex.org/I887968799"],"apc_list":null,"apc_paid":null,"fwci":0.2555,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.55613413,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":"71","issue":"3","first_page":"1581","last_page":"1585"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.776718020439148},{"id":"https://openalex.org/keywords/vernier-scale","display_name":"Vernier scale","score":0.7650023698806763},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5561639666557312},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5341749787330627},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.5237229466438293},{"id":"https://openalex.org/keywords/dynamic-range","display_name":"Dynamic range","score":0.5093642473220825},{"id":"https://openalex.org/keywords/snapshot","display_name":"Snapshot (computer storage)","score":0.5009067058563232},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4803382158279419},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4590228497982025},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.4446205794811249},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.42769619822502136},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35622358322143555},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30526313185691833},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2760846018791199},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.23930352926254272},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.20584627985954285},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.1289709210395813}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.776718020439148},{"id":"https://openalex.org/C69710193","wikidata":"https://www.wikidata.org/wiki/Q14946576","display_name":"Vernier scale","level":2,"score":0.7650023698806763},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5561639666557312},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5341749787330627},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.5237229466438293},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.5093642473220825},{"id":"https://openalex.org/C55282118","wikidata":"https://www.wikidata.org/wiki/Q252683","display_name":"Snapshot (computer storage)","level":2,"score":0.5009067058563232},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4803382158279419},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4590228497982025},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.4446205794811249},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.42769619822502136},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35622358322143555},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30526313185691833},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2760846018791199},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.23930352926254272},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.20584627985954285},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.1289709210395813},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2023.3343470","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2023.3343470","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1544882865","https://openalex.org/W2062952706","https://openalex.org/W2120912680","https://openalex.org/W2163630970","https://openalex.org/W2177833654","https://openalex.org/W2180973527","https://openalex.org/W2740439651","https://openalex.org/W2785102225","https://openalex.org/W3145887276","https://openalex.org/W4211122635"],"related_works":["https://openalex.org/W3158414702","https://openalex.org/W4389545333","https://openalex.org/W2296652335","https://openalex.org/W2182982459","https://openalex.org/W2112856903","https://openalex.org/W2541226935","https://openalex.org/W2120912680","https://openalex.org/W1984418134","https://openalex.org/W3022509112","https://openalex.org/W2547517791"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,58,63,72],"135":[4],"ps":[5,9],"dynamic":[6],"range,":[7],"5.45":[8],"effective":[10],"resolution":[11],"2D":[12],"Vernier":[13],"time-to-digital":[14],"converter":[15],"for":[16],"use":[17],"in":[18,71],"an":[19],"all-digital":[20],"phase-locked-loop.":[21],"The":[22,66],"matrix":[23],"readout":[24],"array":[25],"limits":[26],"the":[27,38,49],"number":[28],"of":[29,37],"delay":[30,39],"cells":[31],"necessary":[32],"by":[33],"using":[34],"all":[35],"taps":[36],"lines.":[40],"A":[41],"full":[42],"calibration":[43],"scheme":[44],"is":[45,69],"presented.":[46],"It":[47],"calibrates":[48],"system":[50],"against":[51],"PVT":[52],"variations":[53],"and":[54,56,77,86],"maintains":[55],"favors":[57],"linear":[59],"operation":[60],"over":[61],"achieving":[62],"specified":[64],"resolution.":[65],"proposed":[67],"architecture":[68],"fabricated":[70],"28":[73],"nm":[74],"CMOS":[75],"technology":[76],"consumes":[78],"360":[79],"\u03bcW":[80],"at":[81],"0.9":[82],"V":[83],"supply":[84],"voltage":[85],"55":[87],"MS/s":[88],"conversion":[89],"rate.":[90]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}