{"id":"https://openalex.org/W4389331430","doi":"https://doi.org/10.1109/tcsii.2023.3339622","title":"OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support","display_name":"OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support","publication_year":2023,"publication_date":"2023-12-05","ids":{"openalex":"https://openalex.org/W4389331430","doi":"https://doi.org/10.1109/tcsii.2023.3339622"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2023.3339622","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2023.3339622","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039548811","display_name":"Qingyu Guo","orcid":"https://orcid.org/0000-0002-8509-3933"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Qingyu Guo","raw_affiliation_strings":["Key Laboratory of Microelectronic Devices and Circuits (MoE), School of Integrated Circuits, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronic Devices and Circuits (MoE), School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079795223","display_name":"Nanbing Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Nanbing Pan","raw_affiliation_strings":["Key Laboratory of Microelectronic Devices and Circuits (MoE), School of Integrated Circuits, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronic Devices and Circuits (MoE), School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040563637","display_name":"Xin Qiao","orcid":"https://orcid.org/0000-0003-1438-2348"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xin Qiao","raw_affiliation_strings":["Key Laboratory of Microelectronic Devices and Circuits (MoE), School of Integrated Circuits, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronic Devices and Circuits (MoE), School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048410928","display_name":"Xiaoxin Cui","orcid":"https://orcid.org/0000-0002-0394-8839"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoxin Cui","raw_affiliation_strings":["Key Laboratory of Microelectronic Devices and Circuits (MoE), School of Integrated Circuits, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronic Devices and Circuits (MoE), School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002438548","display_name":"Yuan Wang","orcid":"https://orcid.org/0000-0002-4951-4286"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuan Wang","raw_affiliation_strings":["Key Laboratory of Microelectronic Devices and Circuits (MoE), School of Integrated Circuits, the Beijing Laboratory of Future IC Technology and Science, and the Beijing Advanced Innovation Center for Integrated Circuits, Peking University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronic Devices and Circuits (MoE), School of Integrated Circuits, the Beijing Laboratory of Future IC Technology and Science, and the Beijing Advanced Innovation Center for Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5039548811"],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":0.2681,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.55761665,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":"71","issue":"4","first_page":"1899","last_page":"1903"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7667667865753174},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5001068115234375},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47515106201171875},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40423089265823364},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23370260000228882}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7667667865753174},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5001068115234375},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47515106201171875},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40423089265823364},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23370260000228882}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2023.3339622","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2023.3339622","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6800000071525574}],"awards":[{"id":"https://openalex.org/G927165947","display_name":null,"funder_award_id":"U20A20204","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2097117768","https://openalex.org/W2112796928","https://openalex.org/W2194775991","https://openalex.org/W2604319603","https://openalex.org/W2884071170","https://openalex.org/W2966524683","https://openalex.org/W3118608800","https://openalex.org/W3135701542","https://openalex.org/W3205311052","https://openalex.org/W4220673325","https://openalex.org/W4313024023","https://openalex.org/W4372054923","https://openalex.org/W6787972765","https://openalex.org/W6810983866"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W4392590355","https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W1976168335","https://openalex.org/W2109451123"],"abstract_inverted_index":{"Computing-in-memory":[0],"(CIM)":[1],"has":[2],"emerged":[3],"as":[4],"a":[5,51,63,87],"promising":[6],"architecture":[7],"for":[8],"energy-efficient":[9],"edge":[10],"neural":[11,101],"network":[12],"inference.":[13],"While":[14],"CIM":[15,53],"designs":[16,38],"have":[17],"shown":[18],"great":[19],"potential":[20],"to":[21,40,67,80,103],"benefit":[22],"from":[23],"sparsity,":[24,71],"there":[25],"are":[26],"still":[27],"limitations":[28],"in":[29,36],"supporting":[30],"output":[31,69],"analog-digital":[32],"conversion":[33],"(ADC)":[34],"sparsity":[35],"current":[37],"due":[39],"redundant":[41],"circuits":[42],"and":[43,106,112,117],"weight-refreshing":[44],"overhead.":[45,75],"In":[46],"this":[47],"brief,":[48],"we":[49],"propose":[50],"novel":[52],"design":[54,77],"called":[55],"OASIS":[56,61],"(Output":[57],"Activation":[58],"SparsIty":[59],"Support).":[60],"employs":[62],"single-bit-line":[64],"computation":[65],"circuit":[66],"support":[68],"ADC":[70],"avoiding":[72],"redundancy":[73],"or":[74],"Our":[76],"achieves":[78],"up":[79],"812.2":[81],"TOPS/W":[82],"normalized":[83],"energy":[84],"efficiency":[85],"at":[86],"typical":[88],"50%":[89],"sparsity.":[90],"We":[91],"demonstrate":[92],"its":[93],"effectiveness":[94],"by":[95],"deploying":[96],"all":[97],"layers":[98],"of":[99],"quantized":[100],"networks":[102],"the":[104,110],"chip":[105],"evaluating":[107],"them":[108],"on":[109],"MNIST":[111],"CIFAR-10":[113],"datasets,":[114],"achieving":[115],"99.20%":[116],"84.33%":[118],"accuracy,":[119],"respectively.":[120]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}