{"id":"https://openalex.org/W4389076363","doi":"https://doi.org/10.1109/tcsii.2023.3337119","title":"An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations","display_name":"An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations","publication_year":2023,"publication_date":"2023-11-28","ids":{"openalex":"https://openalex.org/W4389076363","doi":"https://doi.org/10.1109/tcsii.2023.3337119"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2023.3337119","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2023.3337119","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039314767","display_name":"Feng Wei","orcid":"https://orcid.org/0000-0002-7676-7596"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210136793","display_name":"Peng Cheng Laboratory","ror":"https://ror.org/03qdqbt06","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210136793"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Feng Wei","raw_affiliation_strings":["Key Laboratory of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, China","Department of Networked Intelligence, Peng Cheng Laboratory, Shenzhen, China"],"raw_orcid":"https://orcid.org/0000-0002-7676-7596","affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"Department of Networked Intelligence, Peng Cheng Laboratory, Shenzhen, China","institution_ids":["https://openalex.org/I4210136793"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050097039","display_name":"Xiaole Cui","orcid":"https://orcid.org/0000-0002-3382-3703"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210136793","display_name":"Peng Cheng Laboratory","ror":"https://ror.org/03qdqbt06","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210136793"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaole Cui","raw_affiliation_strings":["Key Laboratory of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, China","Department of Networked Intelligence, Peng Cheng Laboratory, Shenzhen, China"],"raw_orcid":"https://orcid.org/0000-0002-3382-3703","affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]},{"raw_affiliation_string":"Department of Networked Intelligence, Peng Cheng Laboratory, Shenzhen, China","institution_ids":["https://openalex.org/I4210136793"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062370793","display_name":"Sunrui Zhang","orcid":"https://orcid.org/0009-0000-9539-1427"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Sunrui Zhang","raw_affiliation_strings":["Key Laboratory of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, China"],"raw_orcid":"https://orcid.org/0009-0000-9539-1427","affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100399154","display_name":"Xing Zhang","orcid":"https://orcid.org/0000-0003-2699-2637"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210136793","display_name":"Peng Cheng Laboratory","ror":"https://ror.org/03qdqbt06","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210136793"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xing Zhang","raw_affiliation_strings":["Department of Networked Intelligence, Peng Cheng Laboratory, Shenzhen, China","School of Integrated Circuits, Peking University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Networked Intelligence, Peng Cheng Laboratory, Shenzhen, China","institution_ids":["https://openalex.org/I4210136793"]},{"raw_affiliation_string":"School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.276,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.95331509,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":99},"biblio":{"volume":"71","issue":"4","first_page":"2329","last_page":"2333"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.661013126373291},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4870198369026184},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4778822958469391},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4156225323677063},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3494989275932312},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3251630365848541},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.3238523006439209},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2302647829055786}],"concepts":[{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.661013126373291},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4870198369026184},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4778822958469391},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4156225323677063},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3494989275932312},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3251630365848541},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.3238523006439209},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2302647829055786},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2023.3337119","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2023.3337119","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7300000190734863}],"awards":[{"id":"https://openalex.org/G5620683156","display_name":null,"funder_award_id":"KQTD 20200820113105004","funder_id":"https://openalex.org/F4320326705","funder_display_name":"Science, Technology and Innovation Commission of Shenzhen Municipality"},{"id":"https://openalex.org/G8303165913","display_name":null,"funder_award_id":"JCYJ20220818100814033","funder_id":"https://openalex.org/F4320326705","funder_display_name":"Science, Technology and Innovation Commission of Shenzhen Municipality"}],"funders":[{"id":"https://openalex.org/F4320326705","display_name":"Science, Technology and Innovation Commission of Shenzhen Municipality","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W2062143991","https://openalex.org/W2117207900","https://openalex.org/W2331783522","https://openalex.org/W2591601611","https://openalex.org/W2775637085","https://openalex.org/W2790511620","https://openalex.org/W2790556218","https://openalex.org/W2896100628","https://openalex.org/W2904299207","https://openalex.org/W2922487710","https://openalex.org/W2966524683","https://openalex.org/W2976137532","https://openalex.org/W3011368285","https://openalex.org/W3104353813","https://openalex.org/W3126970610","https://openalex.org/W3133754064","https://openalex.org/W3159353913"],"related_works":["https://openalex.org/W4392590355","https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W1976168335","https://openalex.org/W2109451123","https://openalex.org/W4378977321","https://openalex.org/W3211992815","https://openalex.org/W179354024"],"abstract_inverted_index":{"The":[0,103],"in-memory":[1,27],"computing":[2],"(IMC)":[3],"architecture":[4],"eliminates":[5],"the":[6,11,15,26,33,37,43,54,75,78,82,86,97,100,111,114,134],"frequent":[7],"data":[8],"transfers":[9],"between":[10,105],"memory":[12],"banks":[13],"and":[14,81,99,121,142,146],"processor":[16],"cores.":[17],"Researchers":[18],"have":[19],"utilized":[20],"different":[21,106],"SRAM":[22,57,63,76,116],"cells":[23],"to":[24],"implement":[25,36],"logic":[28,79,112],"operations.":[29],"However,":[30],"most":[31],"of":[32,119,124],"previous":[34],"works":[35],"column-wise":[38,44,48,98],"logic/CAM":[39,49],"operations,":[40],"which":[41,68],"require":[42],"stored":[45],"operands.":[46],"These":[47],"operations":[50,87],"are":[51],"incompatible":[52],"with":[53,65,128,140],"traditional":[55],"row-wise":[56,101],"mode.":[58],"This":[59],"brief":[60],"proposes":[61],"an":[62],"cell":[64],"11":[66],"transistors,":[67],"can":[69,92,138],"work":[70,139],"in":[71,88,96],"four":[72,90],"operation":[73],"modes:":[74],"mode,":[77,80,113],"BCAM/TCAM":[83,135],"modes.":[84],"All":[85],"these":[89],"modes":[91,107],"be":[93],"performed":[94],"both":[95],"style.":[102],"incompatibility":[104],"is":[108],"eliminated.":[109],"In":[110,133],"proposed":[115],"achieves":[117],"frequency":[118],"595MHz":[120],"energy":[122],"consumption":[123],"17.94fJ/bit":[125],"at":[126,148],"1.2V":[127,149],"TSMC":[129],"65nm":[130],"technology":[131],"file.":[132],"modes,":[136],"it":[137,143],"407MHz,":[141],"consumes":[144],"0.62fJ/bit":[145],"1.38fJ/bit":[147]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":11},{"year":2024,"cited_by_count":3}],"updated_date":"2026-06-19T17:40:00.097472","created_date":"2025-10-10T00:00:00"}
