{"id":"https://openalex.org/W4388953082","doi":"https://doi.org/10.1109/tcsii.2023.3335987","title":"A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique","display_name":"A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique","publication_year":2023,"publication_date":"2023-11-23","ids":{"openalex":"https://openalex.org/W4388953082","doi":"https://doi.org/10.1109/tcsii.2023.3335987"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2023.3335987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2023.3335987","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100388792","display_name":"Jiawei Wang","orcid":"https://orcid.org/0000-0003-3844-2552"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jiawei Wang","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100952024","display_name":"Zhao Gao","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhao Gao","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075507579","display_name":"Xu Cheng","orcid":"https://orcid.org/0000-0002-0314-0178"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xu Cheng","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079852292","display_name":"Jue Wang","orcid":"https://orcid.org/0000-0001-9939-4297"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jue Wang","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100332689","display_name":"Zhen Li","orcid":"https://orcid.org/0009-0007-0739-7572"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhen Li","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066674438","display_name":"Jun Han","orcid":"https://orcid.org/0000-0002-5245-0754"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Han","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100656792","display_name":"Xiaoyang Zeng","orcid":"https://orcid.org/0000-0003-3986-137X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyang Zeng","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5100388792"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.4506,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.59080819,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"71","issue":"4","first_page":"1859","last_page":"1863"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.7120837569236755},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.6297003030776978},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5659189820289612},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5630502104759216},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.4926019310951233},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.4885200262069702},{"id":"https://openalex.org/keywords/metastability","display_name":"Metastability","score":0.4844372570514679},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4650059640407562},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.4283597469329834},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3813370168209076},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3626636266708374},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.306784987449646},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.27608153223991394},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16657701134681702},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10903578996658325}],"concepts":[{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.7120837569236755},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.6297003030776978},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5659189820289612},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5630502104759216},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.4926019310951233},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.4885200262069702},{"id":"https://openalex.org/C89464430","wikidata":"https://www.wikidata.org/wiki/Q849516","display_name":"Metastability","level":2,"score":0.4844372570514679},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4650059640407562},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.4283597469329834},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3813370168209076},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3626636266708374},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.306784987449646},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27608153223991394},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16657701134681702},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10903578996658325},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C74650414","wikidata":"https://www.wikidata.org/wiki/Q11397","display_name":"Classical mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2023.3335987","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2023.3335987","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G2519052758","display_name":null,"funder_award_id":"61934002","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G4369517068","display_name":null,"funder_award_id":"62234008","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1976807891","https://openalex.org/W2076566235","https://openalex.org/W2772829777","https://openalex.org/W2782303535","https://openalex.org/W2785229656","https://openalex.org/W2795591835","https://openalex.org/W2941480133","https://openalex.org/W2985840259","https://openalex.org/W3112638864","https://openalex.org/W3116426759","https://openalex.org/W3159537255","https://openalex.org/W3209003531","https://openalex.org/W4200524632","https://openalex.org/W4293143561","https://openalex.org/W4312759127","https://openalex.org/W4380904165"],"related_works":["https://openalex.org/W4307107610","https://openalex.org/W3213627526","https://openalex.org/W4226159838","https://openalex.org/W631083485","https://openalex.org/W3138976155","https://openalex.org/W1992748572","https://openalex.org/W3102066851","https://openalex.org/W2161636646","https://openalex.org/W4391823081","https://openalex.org/W2109469245"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,56,70],"metastability":[4],"detection":[5],"and":[6,15,36,60,78,109],"escape":[7],"acceleration":[8],"(MDEA)":[9],"technique":[10,94],"to":[11,38,106,118],"enhance":[12],"the":[13,17,61,92,96,100,111],"bandwidth":[14,114],"lower":[16],"switching":[18,97],"power":[19,85,98],"of":[20,99],"successive-approximation":[21],"register":[22],"(SAR)":[23],"analog-to-digital":[24],"converters":[25],"(ADCs).":[26],"It":[27],"is":[28,47],"implemented":[29],"as":[30],"an":[31,39],"AC-coupling":[32],"switched-capacitor":[33],"latch":[34],"(ACC-SCL)":[35],"applied":[37],"8-bit":[40],"4-channel":[41],"time-interleaved":[42],"SAR":[43],"ADC,":[44],"whose":[45],"layout":[46],"synthesized":[48],"automatically.":[49],"The":[50,87],"ADC":[51],"has":[52],"been":[53],"fabricated":[54],"in":[55],"28-nm":[57],"CMOS":[58],"process,":[59],"measurement":[62],"results":[63],"show":[64],"that":[65,91],"it":[66],"achieves":[67],"1.6":[68],"GS/s,":[69],"42.6-dB":[71],"signal-to-noise-and-distortion":[72],"ratio":[73],"(SNDR)":[74],"at":[75],"Nyquist":[76],"input,":[77],"dissipates":[79],"3.22":[80],"mW":[81,105],"from":[82,103,115],"1.0":[83],"V":[84],"supply.":[86],"comparative":[88],"experiments":[89],"indicate":[90],"MDEA":[93],"reduces":[95],"capacitor":[101],"array":[102],"1.20":[104],"0.95":[107],"mW,":[108],"improves":[110],"effective":[112],"resolution":[113],"0.6":[116],"GHz":[117],"0.8":[119],"GHz.":[120]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}